Re: [Xen-devel] [PATCH] tools/libxc: Properly increment ApicIdCoreSize field on AMD

[Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx>]

On 07/22/2016 01:38 PM, Wei Liu wrote:
> On Fri, Jul 22, 2016 at 01:14:01PM -0400, Boris Ostrovsky wrote:
>> Current code incorrectly adds 1 to full register instead of
>> incrementing the field in bits 15:12.
>>
>> Signed-off-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx>
> Acked-by: Wei Liu <wei.liu2@xxxxxxxxxx>
>
> I trust your expertise in this field. :-)


Just in this field? The field is only 4 bits! ;-)

But this actually fixes a regression that was triggered by recent
hvmloader change on one particular processor that we have in the test farm.

-boris

>
>> ---
>>  tools/libxc/xc_cpuid_x86.c | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c
>> index 84f4e08..fbbac9e 100644
>> --- a/tools/libxc/xc_cpuid_x86.c
>> +++ b/tools/libxc/xc_cpuid_x86.c
>> @@ -331,7 +331,8 @@ static void amd_xc_cpuid_policy(xc_interface *xch,
>>           * ECX[15:12] is ApicIdCoreSize: ECX[7:0] is NumberOfCores (minus 
>> one).
>>           * Update to reflect vLAPIC_ID = vCPU_ID * 2.
>>           */
>> -        regs[2] = ((regs[2] & 0xf000u) + 1) | ((regs[2] & 0xffu) << 1) | 1u;
>> +        regs[2] = ((regs[2] + (1u << 12)) & 0xf000u) |
>> +                  ((regs[2] & 0xffu) << 1) | 1u;
>>          break;
>>  
>>      case 0x8000000a: {
>> -- 
>> 1.8.3.1
>>


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