Re: [Xen-devel] [PATCH v4 4/8] monitor: ARM SMC events

[Tamas K Lengyel <tamas@xxxxxxxxxxxxx>]

On Thu, Jun 2, 2016 at 8:23 AM, Julien Grall <julien.grall@xxxxxxx> wrote:
>
> Hello Tamas,
>
> On 01/06/16 16:41, Tamas K Lengyel wrote:
>>
>>
>> On Jun 1, 2016 05:37, "Julien Grall" <julien.grall@xxxxxxx
>> <mailto:julien.grall@xxxxxxx>> wrote:
>>  > On 29/05/16 23:37, Tamas K Lengyel wrote:
>>  >>
>>  >> Add support for monitoring ARM SMC events. This patch only adds the
>> required
>>  >> bits to enable/disable monitoring and forwarding the event through
>> vm_event.
>>  >
>>  >
>>  > Couple of questions:
>>  >
>>  > - How the vm-event app will differentiate a SMC64 vs a SMC32 call?
>>
>> Wouldn't cpsr record the guest state when the smc was executed, telling
>> us whether it was 32bit or 64bit?
>
>
> You are right.
>
>>  > - How the vm-event app will know the SMC number (i.e the
>>  >
>>  > In an AArch64 state, those informations are available from the
>> syndrome register (HSR_EL2.ISS).
>>
>> Good question, it should probably be sent alongside the other registers.
>> At the moment my usecase doesn't care about it as I'm just using SMC for
>> inducing traps to the vmm but other applications may indeed need this.
>
>
> In this case, we should either provide HSR_EL2, or decode it provide the
> value.
>
> Note that HSR_EL2.ISS is unknown for ARMv7 (see B3-1431 in ARM DDI 0406C.c).
>
> On ARMv8, ESR_EL2.ISS has a different encoding depending on the state (i.e
> AArch64 or AArch32). See D7-1861 in ARM DDI 0487A.i. Furthermore, in AArch32
> state, the ARMv8 specs permits to trap conditional SMC instructions that
> fail their condition check (see D7-1897 in ARM DDI 0406C.c).
>
> So I guess, this need to be abstract in Xen to avoid burden to the
> introspection app.

So during the trap ESR_EL2 is already read into const union hsr hsr,
so my thinking was to just submit hsr.iss to the introspection app and
let it deal with decoding it if it needs to.

Tamas

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