[Xen-devel] [PATCH RFC 3/8] libxl: cpuid: add cache core count support

[Joao Martins <joao.m.martins@xxxxxxxxxx>]

Intel Cache Topology info is determinted by the leaf 4
its subleaves. So, Only the core count is exposed as the remaining
info in the subleaves are inherited by the host (e.g. cache size)

Signed-off-by: Joao Martins <joao.m.martins@xxxxxxxxxx>
---
CC: Ian Jackson <ian.jackson@xxxxxxxxxxxxx>
CC: Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>
CC: Ian Campbell <ian.campbell@xxxxxxxxxx>
CC: Wei Liu <wei.liu2@xxxxxxxxxx>
---
 tools/libxl/libxl_cpuid.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/tools/libxl/libxl_cpuid.c b/tools/libxl/libxl_cpuid.c
index c66e912..deb81d2 100644
--- a/tools/libxl/libxl_cpuid.c
+++ b/tools/libxl/libxl_cpuid.c
@@ -187,6 +187,10 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list 
*cpuid, const char* str)
         {"nx",           0x80000001, NA, CPUID_REG_EDX, 20,  1},
         {"syscall",      0x80000001, NA, CPUID_REG_EDX, 11,  1},
         {"procpkg",      0x00000004,  0, CPUID_REG_EAX, 26,  6},
+        {"proccountl1d", 0x00000004,  0, CPUID_REG_EAX, 14, 12},
+        {"proccountl1i", 0x00000004,  1, CPUID_REG_EAX, 14, 12},
+        {"proccountl2",  0x00000004,  2, CPUID_REG_EAX, 14, 12},
+        {"proccountl3",  0x00000004,  3, CPUID_REG_EAX, 14, 12},
         {"apicidsize",   0x80000008, NA, CPUID_REG_ECX, 12,  4},
         {"nc",           0x80000008, NA, CPUID_REG_ECX,  0,  8},
         {"svm_npt",      0x8000000a, NA, CPUID_REG_EDX,  0,  1},
-- 
2.1.4


_______________________________________________
Xen-devel mailing list
Xen-devel@xxxxxxxxxxxxx
http://lists.xen.org/xen-devel