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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCH RFC 09/31] xen/x86: Calculate PV featureset
>>> On 22.12.15 at 18:13, <andrew.cooper3@xxxxxxxxxx> wrote:
> On 22/12/15 17:07, Jan Beulich wrote:
>>>>> On 16.12.15 at 22:24, <andrew.cooper3@xxxxxxxxxx> wrote:
>>> --- a/xen/arch/x86/cpuid/cpuid.c
>>> +++ b/xen/arch/x86/cpuid/cpuid.c
>>> @@ -102,7 +102,11 @@ const uint32_t
>>> known_features[XEN_NR_FEATURESET_ENTRIES]
> =
>>> cpufeat_mask(X86_FEATURE_CAT)
>>>
> |
>>>
> cpufeat_mask(X86_FEATURE_RDSEED) |
>>> cpufeat_mask(X86_FEATURE_ADX)
>>>
> |
>>> -
>>> cpufeat_mask(X86_FEATURE_SMAP)),
>>> + cpufeat_mask(X86_FEATURE_SMAP)
>>>
> |
>>> +
> cpufeat_mask(X86_FEATURE_PCOMMIT) |
>>> +
> cpufeat_mask(X86_FEATURE_CLFLUSHOPT) |
>>> + cpufeat_mask(X86_FEATURE_CLWB)
>>>
> |
>>> + cpufeat_mask(X86_FEATURE_SHA)),
>>>
>>> [cpufeat_word(X86_FEATURE_PREFETCHWT1)] =
> (cpufeat_mask(X86_FEATURE_PREFETCHWT1)),
>>>
>>> @@ -116,6 +120,101 @@ const uint32_t
> inverted_features[XEN_NR_FEATURESET_ENTRIES] =
>>> [cpufeat_word(X86_FEATURE_FPU_SEL)] =
> cpufeat_mask(X86_FEATURE_FPU_SEL),
>>> };
>>>
>>> +#define PV_FEATUREMASK_1d \
>>> + (cpufeat_mask(X86_FEATURE_FPU) | \
>>> + cpufeat_mask(X86_FEATURE_DE) | \
>>> + cpufeat_mask(X86_FEATURE_TSC) | \
>>> + cpufeat_mask(X86_FEATURE_MSR) | \
>>> + cpufeat_mask(X86_FEATURE_PAE) | \
>>> + cpufeat_mask(X86_FEATURE_MCE) | \
>>> + cpufeat_mask(X86_FEATURE_CX8) | \
>>> + cpufeat_mask(X86_FEATURE_APIC) | \
>>> + cpufeat_mask(X86_FEATURE_SEP) | \
>>> + cpufeat_mask(X86_FEATURE_MCA) | \
>>> + cpufeat_mask(X86_FEATURE_CMOV) | \
>>> + cpufeat_mask(X86_FEATURE_PAT) | \
>>> + cpufeat_mask(X86_FEATURE_CLFLSH) | \
>>> + cpufeat_mask(X86_FEATURE_ACPI) | \
>>> + cpufeat_mask(X86_FEATURE_MMX) | \
>>> + cpufeat_mask(X86_FEATURE_FXSR) | \
>>> + cpufeat_mask(X86_FEATURE_XMM) | \
>>> + cpufeat_mask(X86_FEATURE_XMM2))
>>> +
>>> +#define PV_FEATUREMASK_1c \
>>> + (cpufeat_mask(X86_FEATURE_XMM3) | \
>>> + cpufeat_mask(X86_FEATURE_PCLMULQDQ) | \
>>> + cpufeat_mask(X86_FEATURE_SSSE3) | \
>>> + cpufeat_mask(X86_FEATURE_FMA) | \
>>> + cpufeat_mask(X86_FEATURE_CX16) | \
>>> + cpufeat_mask(X86_FEATURE_SSE4_1) | \
>>> + cpufeat_mask(X86_FEATURE_SSE4_2) | \
>>> + cpufeat_mask(X86_FEATURE_X2APIC) | \
>>> + cpufeat_mask(X86_FEATURE_MOVBE) | \
>>> + cpufeat_mask(X86_FEATURE_POPCNT) | \
>>> + cpufeat_mask(X86_FEATURE_AES) | \
>>> + cpufeat_mask(X86_FEATURE_XSAVE) | \
>>> + cpufeat_mask(X86_FEATURE_AVX) | \
>>> + cpufeat_mask(X86_FEATURE_F16C) | \
>>> + cpufeat_mask(X86_FEATURE_RDRAND) | \
>>> + cpufeat_mask(X86_FEATURE_HYPERVISOR))
>>> +
>>> +#define PV_FEATUREMASK_e1d \
>>> + ((PV_FEATUREMASK_1d & SHARED_1d) | \
>>> + cpufeat_mask(X86_FEATURE_SYSCALL) | \
>>> + cpufeat_mask(X86_FEATURE_MP) | \
>>> + cpufeat_mask(X86_FEATURE_NX) | \
>>> + cpufeat_mask(X86_FEATURE_MMXEXT) | \
>>> + cpufeat_mask(X86_FEATURE_FFXSR) | \
>>> + cpufeat_mask(X86_FEATURE_LM) | \
>>> + cpufeat_mask(X86_FEATURE_3DNOWEXT) | \
>>> + cpufeat_mask(X86_FEATURE_3DNOW))
>>> +
>>> +#define PV_FEATUREMASK_e1c \
>>> + (cpufeat_mask(X86_FEATURE_LAHF_LM) | \
>>> + cpufeat_mask(X86_FEATURE_ABM) | \
>>> + cpufeat_mask(X86_FEATURE_SSE4A) | \
>>> + cpufeat_mask(X86_FEATURE_MISALIGNSSE) | \
>>> + cpufeat_mask(X86_FEATURE_3DNOWPREFETCH) | \
>>> + cpufeat_mask(X86_FEATURE_XOP) | \
>>> + cpufeat_mask(X86_FEATURE_LWP) | \
>>> + cpufeat_mask(X86_FEATURE_FMA4) | \
>>> + cpufeat_mask(X86_FEATURE_TBM) | \
>>> + cpufeat_mask(X86_FEATURE_DBEXT))
>>> +
>>> +#define PV_FEATUREMASK_Da1 \
>>> + (cpufeat_mask(X86_FEATURE_XSAVEOPT) | \
>>> + cpufeat_mask(X86_FEATURE_XSAVEC) | \
>>> + cpufeat_mask(X86_FEATURE_XGETBV1))
>>> +
>>> +#define PV_FEATUREMASK_7b0 \
>>> + (cpufeat_mask(X86_FEATURE_FSGSBASE) | \
>>> + cpufeat_mask(X86_FEATURE_BMI1) | \
>>> + cpufeat_mask(X86_FEATURE_HLE) | \
>>> + cpufeat_mask(X86_FEATURE_AVX2) | \
>>> + cpufeat_mask(X86_FEATURE_BMI2) | \
>>> + cpufeat_mask(X86_FEATURE_ERMS) | \
>>> + cpufeat_mask(X86_FEATURE_RTM) | \
>>> + cpufeat_mask(X86_FEATURE_RDSEED) | \
>>> + cpufeat_mask(X86_FEATURE_ADX) | \
>>> + cpufeat_mask(X86_FEATURE_PCOMMIT) | \
>>> + cpufeat_mask(X86_FEATURE_CLFLUSHOPT) | \
>>> + cpufeat_mask(X86_FEATURE_CLWB) | \
>>> + cpufeat_mask(X86_FEATURE_SHA))
>>> +
>>> +#define PV_FEATUREMASK_7c0 \
>>> + (cpufeat_mask(X86_FEATURE_PREFETCHWT1))
>>> +
>>> +const uint32_t pv_featuremask[XEN_NR_FEATURESET_ENTRIES] =
>>> +{
>>> + PV_FEATUREMASK_1d,
>>> + PV_FEATUREMASK_1c,
>>> + PV_FEATUREMASK_e1d,
>>> + PV_FEATUREMASK_e1c,
>>> + PV_FEATUREMASK_Da1,
>>> + PV_FEATUREMASK_7b0,
>>> + PV_FEATUREMASK_7c0,
>>> +};
>> Why single time used #defines rather than directly populating the
>> array, just like done above for known_features[]?
>
> That will become clear with the following patch, where HVM becomes
> strictly an extension of PV.
I've just seen that. However, much of this would be unnecessary
when things got generated from a single table.
Jan
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