Re: [Xen-devel] xhci_hcd intterrupt affinity in Dom0/DomU limited to single interrupt

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 03.09.15 at 14:04, <ackerj67@xxxxxxxxx> wrote:
>>>> On 02.09.15 at 19:17, <ackerj67@xxxxxxxxx> wrote:
>>      From: Jan Beulich <jbeulich@xxxxxxxx>
>>  Sent: Wednesday, September 2, 2015 4:58 AM
>>>>> Justin Acker <ackerj67@xxxxxxxxx> 09/02/15 1:14 AM >>>
>>> 00:14.0 USB controller: Intel Corporation 7 Series/C210 Series Chipset 
> Family USB xHCI Host Controller (rev 04) (prog-if 30 [XHCI])
>>>    Subsystem: Dell Device 053e
>>>    Flags: bus master, medium devsel, latency 0, IRQ 78
>>>    Memory at f7f20000 (64-bit, non-prefetchable) [size=64K]
>>>    Capabilities: [70] Power Management version 2
>>>    Capabilities: [80] MSI: Enable+ Count=1/8 Maskable- 64bit+
>> 
>> This shows that the driver could use up to 8 MSI IRQs, but chose to use just 
> 
>> one. If
>> this is the same under Xen and the native kernel, the driver likely doesn't 
>> know any
>> better. If under native more interrupts are being used, there might be an 
>> issue with
>> Xen specific code in the kernel or hypervisor code. We'd need to see details 
> 
>> to be
>> able to tell.
>> 
>> Please let me know what details I should provide. 

I'd like to emphasize what I said in my previous reply:

> Please, first of all, get your reply style fixed. Just look at the above
> and tell me how a reader should figure which parts of the text were
> written by whom.
>
>[...]
>
>      I am still confused as to whether any device, or in this case xhci_hcd, 
> can use more than one cpu at any given time. My     understanding based on 
> David's response is that it cannot due to the event channel mapping. The 
> device interrupt can be pinned     to a specific cpu by specifying the 
> affinity. I was hoping there was a way to allow the driver's interrupt to be 
> scheduled to     use more than 1 CPU at any given time. 

The problem is that you're mixing up two things: devices and
interrupts. Any individual interrupt can only be serviced by a single
CPU at a time, due to the way event channels get bound. Any
individual device can have more than one interrupt (MSI or MSI-X),
and then each of these interrupts can be serviced on different
CPUs.

Jan


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