[Xen-devel] [PATCH V6 05/10] xen/arm64: gicv3: Use AFF1 when translating ICC_SGI1R_EL1 to cpumask

[Chen Baozi <cbz@xxxxxxxxxx>]

From: Chen Baozi <baozich@xxxxxxxxx>

To support more than 16 vCPUs, we have to calculate cpumask with AFF1
field value in ICC_SGI1R_EL1.

Signed-off-by: Chen Baozi <baozich@xxxxxxxxx>
---
 xen/arch/arm/vgic-v3.c            | 30 ++++++++++++++++++++++++++----
 xen/include/asm-arm/gic_v3_defs.h |  2 ++
 2 files changed, 28 insertions(+), 4 deletions(-)

diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
index 2bf5294..f2b78a4 100644
--- a/xen/arch/arm/vgic-v3.c
+++ b/xen/arch/arm/vgic-v3.c
@@ -972,13 +972,28 @@ write_ignore:
     return 1;
 }
 
-static inline void gicv3_sgir_to_cpumask(cpumask_t *cpumask,
+static inline int gicv3_sgir_to_cpumask(cpumask_t *cpumask,
                                          const register_t sgir)
 {
     unsigned long target_list;
+    uint16_t *target_bitmap;
+    unsigned int aff1;
 
     target_list = sgir & ICH_SGI_TARGETLIST_MASK;
-    bitmap_copy(cpumask_bits(cpumask), &target_list, ICH_SGI_TARGET_BITS);
+    /* We assume that only AFF1 is used in ICC_SGI1R_EL1. */
+    aff1 = (sgir >> ICH_SGI_AFFINITY_LEVEL(1)) & ICH_SGI_AFFx_MASK;
+
+    /* There might be up to 4096 vCPUs with all bits in affinity 1
+     * are used, so we have to check whether it will overflow the
+     * bitmap array of cpumask_t.
+     */
+    if ( ((aff1 + 1) * ICH_SGI_TARGET_BITS) > NR_CPUS )
+        return 1;
+
+    target_bitmap = (uint16_t *)cpumask_bits(cpumask);
+    target_bitmap[aff1] = target_list;
+
+    return 0;
 }
 
 static int vgic_v3_to_sgi(struct vcpu *v, register_t sgir)
@@ -996,8 +1011,15 @@ static int vgic_v3_to_sgi(struct vcpu *v, register_t sgir)
     switch ( irqmode )
     {
     case ICH_SGI_TARGET_LIST:
-        /* SGI's are injected at Rdist level 0. ignoring affinity 1, 2, 3 */
-        gicv3_sgir_to_cpumask(&vcpu_mask, sgir);
+        /*
+         * Currenty we assume only affinity level-1 is used in SGI's
+         * injection, ignoring level 2 & 3.
+         */
+        if ( gicv3_sgir_to_cpumask(&vcpu_mask, sgir) )
+        {
+            gprintk(XENLOG_WARNING, "Wrong affinity in SGI1R_EL register\n");
+            return 0;
+        }
         sgi_mode = SGI_TARGET_LIST;
         break;
     case ICH_SGI_TARGET_OTHERS:
diff --git a/xen/include/asm-arm/gic_v3_defs.h 
b/xen/include/asm-arm/gic_v3_defs.h
index e106e67..333aa56 100644
--- a/xen/include/asm-arm/gic_v3_defs.h
+++ b/xen/include/asm-arm/gic_v3_defs.h
@@ -153,6 +153,8 @@
 #define ICH_SGI_IRQ_MASK             0xf
 #define ICH_SGI_TARGETLIST_MASK      0xffff
 #define ICH_SGI_TARGET_BITS          16
+#define ICH_SGI_AFFx_MASK            0xff
+#define ICH_SGI_AFFINITY_LEVEL(x)    (16 * (x))
 
 #endif /* __ASM_ARM_GIC_V3_DEFS_H__ */
 
-- 
2.1.4


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