Re: [Xen-devel] [RFC PATCH 00/19] xen/arm: Add ITS support

[Vijay Kilari <vijay.kilari@xxxxxxxxx>]

On Fri, Mar 13, 2015 at 3:43 PM, Julien Grall <julien.grall@xxxxxxxxxx> wrote:
> Hi Vijay,
>
> On 13/03/2015 04:48, Vijay Kilari wrote:
>>
>> The changes that I envisage for supporting Multiple ITS is
>>    - Generate as many number of ITS dt nodes for Dom0 that host DT
>> contains.
>>    - For DomU always generate only one ITS node
>>    - vITS will register MMIO handlers for all physical ITS of Dom0, but
>> vITS will only have
>>      one VITS structure per domain. The limitation with this approach
>> is that all vITS requests are
>>      serialized even though there are more than one physical ITS. But
>> this approach makes
>>      implementation simple.
>
>
> Each vITS will have his own command queue... How do you plan to handle it
> with only a single structure?

Yes, I agree with single structure we could not maintain two commad queues

>
> Can you provide an idea what the structure will look like?

Below is the sample structures with description. I will send patch series

struct cid_mapping
{
    /* Number of collections mapped */
    uint8_t nr_cid;
    /* XXX: assume one collection id per vcpu. can set to MAX_VCPUS? */
    /* Virtual collection id */
    uint8_t vcid[32];
    /* Physical collection id */
    uint8_t pcid[32];
    /* Virtual target address of this collection id */
    uint64_t vta[32];
};

struct its_node;

/* Per domain per physical ITS, virtual ITS struct */
struct vgic_its
{
   spinlock_t lock;
   /* Emulation of BASER */
   paddr_t baser[8];
   /* Command queue base */
   paddr_t cmd_base;
   /* Command queue write pointer */
   paddr_t cmd_write;
   /* Command queue write saved pointer */
   paddr_t cmd_write_save;
   /* Command queue read pointer */
   paddr_t cmd_read;
   /* Command queue size */
   unsigned long cmd_qsize;
   /* ITS mmio physical base */
   paddr_t phys_base;
   /* ITS mmio physical size */
   unsigned long phys_size;
   /* gicr ctrl register */
   uint32_t ctrl;
   /* Virtual to Physical Collection id mapping */
   struct cid_mapping cid_map;
};

struct vgic_lpi_conf
{
   /* LPI propbase */
   paddr_t propbase;
   /* percpu pendbase */
   paddr_t pendbase[MAX_VIRT_CPUS];
   /* Virtual LPI property table */
   void * prop_page;
};

/* ITS device structure */
struct vits_device
{
    struct list_head entry;
    /* Virtual ITS node */
    struct vgic_its *vits;
    /* ITS physical node */
    struct its_node *its;
    /* Collection assigned */
    struct its_collection *collection;
    /* Device id */
    uint32_t  dev_id;
    /* ITT address */
    paddr_t itt_addr;
    /* ITT size */
    unsigned long itt_size;
    /* LPIs assigned to device */
    struct list_head hwirq_list;
};

asm-arm/domain.h


struct vgic_its *vits;
struct vgic_lpi_conf *lpi_conf;
struct vits_device {
    spinlock_t lock;
    struct list_head dev_List;
} vits_devs;

Regards
Vijay

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