Re: [Xen-devel] [PATCH v2 3/9] xen: arm: Handle 32-bit EL0 on 64-bit EL1 when advancing PC after trap

[Julien Grall <julien.grall@xxxxxxxxxx>]

Hi Ian,

On 10/02/2015 12:45, Ian Campbell wrote:
> Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
> Reviewed-by: Julien Grall <julien.grall@xxxxxxxxxx>
> ---
>   xen/arch/arm/traps.c |    8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
> index c5f65db..be65862 100644
> --- a/xen/arch/arm/traps.c
> +++ b/xen/arch/arm/traps.c
> @@ -1487,7 +1487,7 @@ static int check_conditional_instr(struct cpu_user_regs 
> *regs, union hsr hsr)
>       {
>           unsigned long it;
>
> -        BUG_ON( !is_32bit_domain(current->domain) || !(cpsr&PSR_THUMB) );
> +        BUG_ON( !psr_mode_is_32bit(regs->cpsr) || !(cpsr&PSR_THUMB) );
>
>           it = ( (cpsr >> (10-2)) & 0xfc) | ((cpsr >> 25) & 0x3 );
>
> @@ -1496,7 +1496,7 @@ static int check_conditional_instr(struct cpu_user_regs 
> *regs, union hsr hsr)
>               return 1;
>
>           /* The cond for this instruction works out as the top 4 bits. */
> -        cond =  ( it >> 4 );
> +        cond = ( it >> 4 );
I haven't spot it in the previous review. This seems to be only a coding 
change. Could you specify it in the commit message?
Regards,

--
Julien Grall

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