Re: [Xen-devel] [PATCH v12 for-xen-4.5 15/20] x86/VPMU: Add support for PMU register handling on PV guests

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 25.09.14 at 21:28, <boris.ostrovsky@xxxxxxxxxx> wrote:
> Intercept accesses to PMU MSRs and process them in VPMU module.
> 
> Dump VPMU state for all domains (HVM and PV) when requested.
> 
> Signed-off-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx>

Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
provided ...

> @@ -2561,7 +2569,22 @@ static int emulate_privileged_op(struct cpu_user_regs 
> *regs)
>              if ( v->arch.debugreg[7] & DR7_ACTIVE_MASK )
>                  wrmsrl(regs->_ecx, msr_content);
>              break;
> -
> +        case MSR_P6_PERFCTR(0)...MSR_P6_PERFCTR(7):
> +        case MSR_P6_EVNTSEL(0)...MSR_P6_EVNTSEL(3):
> +        case MSR_CORE_PERF_FIXED_CTR0...MSR_CORE_PERF_FIXED_CTR2:
> +        case MSR_CORE_PERF_FIXED_CTR_CTRL...MSR_CORE_PERF_GLOBAL_OVF_CTRL:
> +            if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
> +            {
> +                vpmu_msr = 1;
> +        case MSR_AMD_FAM15H_EVNTSEL0...MSR_AMD_FAM15H_PERFCTR5:
> +                if ( vpmu_msr || (boot_cpu_data.x86_vendor == 
> X86_VENDOR_AMD) )
> +                {
> +                    if ( vpmu_do_wrmsr(regs->ecx, msr_content, 0) )
> +                        goto fail;
> +                }
> +                break;
> +            }
> +            /*FALLTHROUGH*/
>          default:
>              if ( wrmsr_hypervisor_regs(regs->ecx, msr_content) == 1 )
>                  break;
> @@ -2593,6 +2616,7 @@ static int emulate_privileged_op(struct cpu_user_regs 
> *regs)
>          break;
>  
>      case 0x32: /* RDMSR */
> +        vpmu_msr = 0;
>          switch ( (u32)regs->ecx )
>          {
>          case MSR_FS_BASE:
> @@ -2663,7 +2687,29 @@ static int emulate_privileged_op(struct cpu_user_regs 
> *regs)
>                              [regs->_ecx - MSR_AMD64_DR1_ADDRESS_MASK + 1];
>              regs->edx = 0;
>              break;
> +        case MSR_IA32_PERF_CAPABILITIES:
> +            /* No extra capabilities are supported */
> +            regs->eax = regs->edx = 0;
> +            break;
> +        case MSR_P6_PERFCTR(0)...MSR_P6_PERFCTR(7):
> +        case MSR_P6_EVNTSEL(0)...MSR_P6_EVNTSEL(3):
> +        case MSR_CORE_PERF_FIXED_CTR0...MSR_CORE_PERF_FIXED_CTR2:
> +        case MSR_CORE_PERF_FIXED_CTR_CTRL...MSR_CORE_PERF_GLOBAL_OVF_CTRL:
> +            if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
> +            {
> +                vpmu_msr = 1;
> +        case MSR_AMD_FAM15H_EVNTSEL0...MSR_AMD_FAM15H_PERFCTR5:
> +                if ( vpmu_msr || (boot_cpu_data.x86_vendor == 
> X86_VENDOR_AMD) )
> +                {
> +                    if ( vpmu_do_rdmsr(regs->ecx, &msr_content) )
> +                        goto fail;
>  
> +                    regs->eax = (uint32_t)msr_content;
> +                    regs->edx = (uint32_t)(msr_content >> 32);
> +                }
> +                break;
> +            }
> +            /*FALLTHROUGH*/
>          default:
>              if ( rdmsr_hypervisor_regs(regs->ecx, &val) )
>              {

... you retain the blank lines and suitably add another one in each
code chunk.

Jan


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