Re: [Xen-devel] [PATCH v9 14/20] x86/VPMU: Add support for PMU register handling on PV guests

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 08.08.14 at 18:55, <boris.ostrovsky@xxxxxxxxxx> wrote:
> @@ -2556,7 +2564,22 @@ static int emulate_privileged_op(struct cpu_user_regs 
> *regs)
>              if ( v->arch.debugreg[7] & DR7_ACTIVE_MASK )
>                  wrmsrl(regs->_ecx, msr_content);
>              break;
> -
> +        case MSR_P6_PERFCTR0...MSR_P6_PERFCTR1:
> +        case MSR_P6_EVNTSEL0...MSR_P6_EVNTSEL1:
> +        case MSR_CORE_PERF_FIXED_CTR0...MSR_CORE_PERF_FIXED_CTR2:
> +        case MSR_CORE_PERF_FIXED_CTR_CTRL...MSR_CORE_PERF_GLOBAL_OVF_CTRL:
> +            if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
> +                vpmu_msr = 1;
> +            /* FALLTHROUGH */
> +        case MSR_AMD_FAM15H_EVNTSEL0...MSR_AMD_FAM15H_PERFCTR5:
> +            if ( vpmu_msr ||
> +                 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !vpmu_msr) 
> )

Pointlessly complicated right side of the ||: (a || (b && !a)) is the same
as (a || b). Meaning this _still_ doesn't achieve what you appear to
want, i.e. the set of Intel MSRs continues to also get handled on AMD
CPUs.

Jan


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