Re: [Xen-devel] [PATCH v2] xen/arm: Trap and yield on WFE instructions

[Ian Campbell <Ian.Campbell@xxxxxxxxxx>]

On Wed, 2014-07-16 at 16:02 +0530, Anup Patel wrote:
> If we have a Guest/DomU with two or more of its VCPUs running
> on same host CPU then it can quite likely happen that these
> VCPUs fight for same spinlock and one of them will waste CPU
> cycles in WFE instruction. This patch makes WFE instruction
> trap for VCPU and forces VCPU to yield its timeslice.
> 
> The KVM ARM/ARM64 also does similar thing for handling WFE
> instructions. (Please refer,
> https://lists.cs.columbia.edu/pipermail/kvmarm/2013-November/006259.html)
> 
> In general, this patch is more of an optimization for an
> oversubscribed system having number of VCPUs more than
> underlying host CPUs.
> 
> Changes since V1:
>  - Added separate member in union hsr for decoding WFI/WFE
>    related info.
> 
> Signed-off-by: Anup Patel <anup.patel@xxxxxxxxxx>
> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@xxxxxxxxxx>
> Tested-by: Pranavkumar Sawargaonkar <pranavkumar@xxxxxxxxxx>

Acked + applied. There was a conflict with "[PATCH v4 1/2] xen/arm :
Adding helper function for WFI" which I just applied before it. I fixed
it up and the result is below, please check it is ok.

I also nuked a hard tab which had snuck in.

Ian.

commit af82c49116c7bf6857be6bf6b56094b9eb2ef012
Author: Anup Patel <anup.patel@xxxxxxxxxx>
Date:   Wed Jul 16 16:02:15 2014 +0530

    xen/arm: Trap and yield on WFE instructions
    
    If we have a Guest/DomU with two or more of its VCPUs running
    on same host CPU then it can quite likely happen that these
    VCPUs fight for same spinlock and one of them will waste CPU
    cycles in WFE instruction. This patch makes WFE instruction
    trap for VCPU and forces VCPU to yield its timeslice.
    
    The KVM ARM/ARM64 also does similar thing for handling WFE
    instructions. (Please refer,

https://lists.cs.columbia.edu/pipermail/kvmarm/2013-November/006259.html)
    
    In general, this patch is more of an optimization for an
    oversubscribed system having number of VCPUs more than
    underlying host CPUs.
    
    Signed-off-by: Anup Patel <anup.patel@xxxxxxxxxx>
    Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@xxxxxxxxxx>
    Tested-by: Pranavkumar Sawargaonkar <pranavkumar@xxxxxxxxxx>
    Acked-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
    [ ijc -- resolved conflict with "Adding helper function for WFI",
             nuked stray hard tab ]

diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 5e4c837..3dfabd0 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -90,7 +90,7 @@ void __cpuinit init_traps(void)
 
     /* Setup hypervisor traps */
     WRITE_SYSREG(HCR_PTW|HCR_BSU_INNER|HCR_AMO|HCR_IMO|HCR_FMO|HCR_VM|
-                 HCR_TWI|HCR_TSC|HCR_TAC|HCR_SWIO|HCR_TIDCP, HCR_EL2);
+                 HCR_TWE|HCR_TWI|HCR_TSC|HCR_TAC|HCR_SWIO|HCR_TIDCP,
HCR_EL2);
     isb();
 }
 
@@ -1803,8 +1803,13 @@ asmlinkage void do_trap_hypervisor(struct
cpu_user_regs *regs)
             advance_pc(regs, hsr);
             return;
         }
-        /* at the moment we only trap WFI */
-        vcpu_block_unless_event_pending(current);
+        if ( hsr.wfi_wfe.ti ) {
+            /* Yield the VCPU for WFE */
+            vcpu_force_reschedule(current);
+        } else {
+            /* Block the VCPU for WFI */
+            vcpu_block_unless_event_pending(current);
+        }
         advance_pc(regs, hsr);
         break;
     case HSR_EC_CP15_32:
diff --git a/xen/include/asm-arm/processor.h
b/xen/include/asm-arm/processor.h
index bdfff4e..9d230f3 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -276,6 +276,15 @@ union hsr {
         unsigned long ec:6;    /* Exception Class */
     } cond;
 
+    struct hsr_wfi_wfe {
+        unsigned long ti:1;    /* Trapped instruction */
+        unsigned long sbzp:19;
+        unsigned long cc:4;    /* Condition Code */
+        unsigned long ccvalid:1;/* CC Valid */
+        unsigned long len:1;   /* Instruction length */
+        unsigned long ec:6;    /* Exception Class */
+    } wfi_wfe;
+
     /* reg, reg0, reg1 are 4 bits on AArch32, the fifth bit is sbzp. */
     struct hsr_cp32 {
         unsigned long read:1;  /* Direction */




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