Re: [Xen-devel] [PATCH v2 1/3] xen/arm: Add 4-level page table for stage 2 translation

[Vijay Kilari <vijay.kilari@xxxxxxxxx>]

On Wed, Jul 16, 2014 at 6:05 PM, Ian Campbell <Ian.Campbell@xxxxxxxxxx> wrote:
> On Wed, 2014-07-16 at 17:12 +0530, Vijay Kilari wrote:
>> On Tue, Jul 15, 2014 at 7:17 PM, Ian Campbell <Ian.Campbell@xxxxxxxxxx> 
>> wrote:
>> > On Tue, 2014-05-27 at 12:16 +0530, vijay.kilari@xxxxxxxxx wrote:
>> >> From: Vijaya Kumar K <Vijaya.Kumar@xxxxxxxxxxxxxxxxxx>
>> >>
>> >> To support 48-bit Physical Address support, add 4-level
>> >> page tables for stage 2 translation.
>> >> With this patch stage 1 and stage 2 translation at EL2 are
>> >> with 4-levels
>> >
>> > I've been playing with this patch on various platforms and unfortunately
>> > there is a rather large snag here, AFAICT. Which is that 4-level stage 2
>> > pages are only available when ID_AA64MMFR0_EL1.PARange >= 44 bits, see
>> > table D4-5 in the ARMv8 ARM.
>>
>>  I read from "Table D5-18 Properties of the address lookup levels, 4KB
>> granule size"
>> Where the lookup level and granule size details are provided. For
>> above 39 bit PA
>> zero level is used.
>
> This is D4-19 in my copy -- OOI which version of the ARM are you working
> from? Mine is ARM DDI0487A.B.

   I am using ARM DDI 0487A.a-1 version. Now I downloaded .B version

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