Re: [Xen-devel] [PATCH v7 5/6] xen/arm: physical irq follow virtual irq

[Ian Campbell <Ian.Campbell@xxxxxxxxxx>]

On Fri, 2014-07-04 at 11:51 +0100, Julien Grall wrote:
> On 07/03/2014 05:53 PM, Stefano Stabellini wrote:
> > diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
> > index 695c232..c3d2853 100644
> > --- a/xen/arch/arm/gic-v2.c
> > +++ b/xen/arch/arm/gic-v2.c
> > @@ -532,9 +532,22 @@ static void gicv2_guest_irq_end(struct irq_desc *desc)
> >      /* Deactivation happens in maintenance interrupt / via GICV */
> >  }
> >  
> > -static void gicv2_irq_set_affinity(struct irq_desc *desc, const cpumask_t 
> > *mask)
> > +static void gicv2_irq_set_affinity(struct irq_desc *desc, const cpumask_t 
> > *cpu_mask)
> >  {
> > -    BUG();
> > +    volatile unsigned char *bytereg;
> > +    unsigned int mask;
> > +
> > +    ASSERT(!cpumask_empty(cpu_mask));
> > +
> > +    spin_lock(&gicv2.lock);
> > +
> > +    mask = gicv2_cpu_mask(cpu_mask);
> > +
> > +    /* Set target CPU mask (RAZ/WI on uniprocessor) */
> > +    bytereg = (unsigned char *) (GICD + GICD_ITARGETSR);
> > +    bytereg[desc->irq] = mask;
> 
> The new implemenation of GICv2 is using {read,write}* helpers. Can you
> use writeb_relaxed here, please?

Now called writeb_gicd(mask, GICD_ITARGETSR + desc->irq) in staging...

Ian.


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