|
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH v01 2/3] xen/arm: add platform specific definitions for DRA7 evm board
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@xxxxxxxxxxxxxxx>
---
xen/arch/arm/platforms/Makefile | 1 +
xen/arch/arm/platforms/dra7xx.c | 158 +++++++++++++++++++++++++++++++
xen/include/asm-arm/platforms/dra7xx.h | 163 ++++++++++++++++++++++++++++++++
3 files changed, 322 insertions(+)
create mode 100644 xen/arch/arm/platforms/dra7xx.c
create mode 100644 xen/include/asm-arm/platforms/dra7xx.h
diff --git a/xen/arch/arm/platforms/Makefile b/xen/arch/arm/platforms/Makefile
index 680364f..080ea9a 100644
--- a/xen/arch/arm/platforms/Makefile
+++ b/xen/arch/arm/platforms/Makefile
@@ -2,5 +2,6 @@ obj-y += vexpress.o
obj-$(CONFIG_ARM_32) += exynos5.o
obj-$(CONFIG_ARM_32) += midway.o
obj-$(CONFIG_ARM_32) += omap5.o
+obj-$(CONFIG_ARM_32) += dra7xx.o
obj-$(CONFIG_ARM_32) += sunxi.o
obj-$(CONFIG_ARM_64) += xgene-storm.o
diff --git a/xen/arch/arm/platforms/dra7xx.c b/xen/arch/arm/platforms/dra7xx.c
new file mode 100644
index 0000000..590d313
--- /dev/null
+++ b/xen/arch/arm/platforms/dra7xx.c
@@ -0,0 +1,158 @@
+/*
+ * xen/arch/arm/platforms/dra7.c
+ *
+ * TI DRA7 specific settings
+ *
+ * Andrii Anisov <andrii.anisov@xxxxxxxxxxxxxxx>
+ * Andrii Tseglytskyi <andrii.tseglytskyi@xxxxxxxxxxxxxxx>
+ * Alexander Savchenko <oleksandr.savchenko@xxxxxxxxxxxxxxx>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <xen/mm.h>
+#include <xen/vmap.h>
+#include <asm/platforms/dra7xx.h>
+#include <asm/platform.h>
+#include <asm/io.h>
+
+static uint16_t num_den[8][2] = {
+ { 0, 0 }, /* not used */
+ { 26 * 64, 26 * 125 }, /* 12.0 Mhz */
+ { 2 * 768, 2 * 1625 }, /* 13.0 Mhz */
+ { 0, 0 }, /* not used */
+ { 130 * 8, 130 * 25 }, /* 19.2 Mhz */
+ { 2 * 384, 2 * 1625 }, /* 26.0 Mhz */
+ { 3 * 256, 3 * 1125 }, /* 27.0 Mhz */
+ { 130 * 4, 130 * 25 }, /* 38.4 Mhz */
+};
+
+/*
+ * The realtime counter also called master counter, is a free-running
+ * counter, which is related to real time. It produces the count used
+ * by the CPU local timer peripherals in the MPU cluster. The timer counts
+ * at a rate of 6.144 MHz. Because the device operates on different clocks
+ * in different power modes, the master counter shifts operation between
+ * clocks, adjusting the increment per clock in hardware accordingly to
+ * maintain a constant count rate.
+ */
+static int dra7_init_time(void)
+{
+ void __iomem *ckgen_prm_base;
+ void __iomem *rt_ct_base;
+ unsigned int sys_clksel;
+ unsigned int num, den, frac1, frac2;
+
+ ckgen_prm_base = ioremap_nocache(DRA7_CKGEN_PRM_BASE, 0x20);
+ if ( !ckgen_prm_base )
+ {
+ dprintk(XENLOG_ERR, "%s: PRM_BASE ioremap failed\n", __func__);
+ return -ENOMEM;
+ }
+
+ sys_clksel = readl(ckgen_prm_base + DRA7_CM_CLKSEL_SYS) &
+ ~SYS_CLKSEL_MASK;
+
+ iounmap(ckgen_prm_base);
+
+ rt_ct_base = ioremap_nocache(REALTIME_COUNTER_BASE, 0x20);
+ if ( !rt_ct_base )
+ {
+ dprintk(XENLOG_ERR, "%s: REALTIME_COUNTER_BASE ioremap failed\n",
__func__);
+ return -ENOMEM;
+ }
+
+ frac1 = readl(rt_ct_base + INCREMENTER_NUMERATOR_OFFSET);
+ num = frac1 & ~NUMERATOR_DENUMERATOR_MASK;
+ if ( num_den[sys_clksel][0] != num )
+ {
+ frac1 &= NUMERATOR_DENUMERATOR_MASK;
+ frac1 |= num_den[sys_clksel][0];
+ }
+
+ frac2 = readl(rt_ct_base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
+ den = frac2 & ~NUMERATOR_DENUMERATOR_MASK;
+ if ( num_den[sys_clksel][1] != num )
+ {
+ frac2 &= NUMERATOR_DENUMERATOR_MASK;
+ frac2 |= num_den[sys_clksel][1];
+ }
+
+ writel(frac1, rt_ct_base + INCREMENTER_NUMERATOR_OFFSET);
+ writel(frac2 | PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD,
+ rt_ct_base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
+
+ iounmap(rt_ct_base);
+
+ return 0;
+}
+
+static int __init dra7_smp_init(void)
+{
+ void __iomem *wugen_base;
+
+ wugen_base = ioremap_nocache(DRA7_WKUPGEN_BASE, PAGE_SIZE);
+ if ( !wugen_base )
+ {
+ dprintk(XENLOG_ERR, "Unable to map omap5 MMIO\n");
+ return -EFAULT;
+ }
+#ifndef NDEBUG
+ printk("Set AuxCoreBoot1 to %"PRIpaddr" (%p)\n",
+ __pa(init_secondary), init_secondary);
+#endif
+ writel(__pa(init_secondary), wugen_base + DRA7_AUX_CORE_BOOT_1_OFFSET);
+#ifndef NDEBUG
+ printk("Set AuxCoreBoot0 to 0x20\n");
+#endif
+ writel(0x20, wugen_base + DRA7_AUX_CORE_BOOT_0_OFFSET);
+
+ iounmap(wugen_base);
+
+ return 0;
+}
+
+static const char const *dra7_dt_compat[] __initdata =
+{
+ "ti,dra7",
+ NULL
+};
+
+static const struct dt_device_match dra7xx_blacklist_dev[] __initconst =
+{
+ /* OMAP Linux kernel handles devices with status "disabled" in a
+ * weird manner - tries to reset them. While their memory ranges
+ * are not mapped, this leads to data aborts, so skip these devices
+ * from DT for dom0.
+ */
+ DT_MATCH_NOT_AVAILABLE(),
+ { /* sentinel */ },
+};
+
+PLATFORM_START(dra7, "TI DRA7")
+ .compatible = dra7_dt_compat,
+ .init_time = dra7_init_time,
+ .cpu_up = cpu_up_send_sgi,
+ .smp_init = dra7_smp_init,
+
+ .dom0_gnttab_start = 0x4b000000,
+ .dom0_gnttab_size = 0x20000,
+ .blacklist_dev = dra7xx_blacklist_dev,
+PLATFORM_END
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/asm-arm/platforms/dra7xx.h
b/xen/include/asm-arm/platforms/dra7xx.h
new file mode 100644
index 0000000..4dec09d
--- /dev/null
+++ b/xen/include/asm-arm/platforms/dra7xx.h
@@ -0,0 +1,163 @@
+#ifndef __ASM_ARM_PLATFORMS_DRA7XX_H
+#define __ASM_ASM_PLATFORMS_DRA7XX_H
+
+#define DRA7_MPU_BOOT_ROM 0x40038000
+#define DRA7_MPU_BOOT_ROM_END 0x40043FFF
+#define DRA7_MPU_BOOT_SRAM 0x402F0000
+#define DRA7_MPU_BOOT_SRAM_END 0x402FFFFF
+#define DRA7_OCMC_RAM1 0x40300000
+#define DRA7_OCMC_RAM1_END 0x4037FFFF
+#define DRA7_OCMC_RAM2 0x40400000
+#define DRA7_OCMC_RAM2_END 0x404FFFFF
+#define DRA7_OCMC_RAM3 0x40500000
+#define DRA7_OCMC_RAM3_END 0x405FFFFF
+#define DRA7_DSP1_L2_RAM 0x40800000
+#define DRA7_DSP1_L2_RAM_END 0x40847FFF
+#define DRA7_DSP1 0x40D00000
+#define DRA7_DSP1_END 0x40D07FFF
+#define DRA7_DSP1_EDMA_CC 0x40D10000
+#define DRA7_DSP1_EDMA_CC_END 0x40D17FFF
+#define DRA7_DSP1_L1P_CACHE 0x40E00000
+#define DRA7_DSP1_L1P_CACHE_END 0x40E07FFF
+#define DRA7_DSP1_L1D_CACHE 0x40F00000
+#define DRA7_DSP1_L1D_CACHE_END 0x40F07FFF
+#define DRA7_DSP2_L2_RAM 0x41000000
+#define DRA7_DSP2_L2_RAM_END 0x41047FFF
+#define DRA7_DSP2 0x41500000
+#define DRA7_DSP2_END 0x41507FFF
+#define DRA7_DSP2_EDMA_CC 0x41510000
+#define DRA7_DSP2_EDMA_CC_END 0x41517FFF
+#define DRA7_DSP2_L1P_CACHE 0x41600000
+#define DRA7_DSP2_L1P_CACHE_END 0x41607FFF
+#define DRA7_DSP2_L1D_CACHE 0x41700000
+#define DRA7_DSP2_L1D_CACHE_END 0x41707FFF
+#define DRA7_OCMC_RAM1_CBUF 0x41800000
+#define DRA7_OCMC_RAM1_CBUF_END 0x41FFFFFF
+#define DRA7_EVE1 0x42000000
+#define DRA7_EVE1_END 0x420FFFFF
+#define DRA7_EVE2 0x42100000
+#define DRA7_EVE2_END 0x421FFFFF
+#define DRA7_EDMA 0x43300000
+#define DRA7_EDMA_END 0x435FFFFF
+#define DRA7_L3_MAIN 0x44000000
+#define DRA7_L3_MAIN_END 0x457FFFFF
+#define DRA7_MCASP1 0x45800000
+#define DRA7_MCASP1_END 0x45BFFFFF
+#define DRA7_MCASP2 0x45C00000
+#define DRA7_MCASP2_END 0x45CFFFFF
+#define DRA7_MCASP3 0x46000000
+#define DRA7_MCASP3_END 0x463FFFFF
+#define DRA7_VCP1 0x46400000
+#define DRA7_VCP1_END 0x4640FFFF
+#define DRA7_VCP2 0x46800000
+#define DRA7_VCP2_END 0x4680FFFF
+#define DRA7_MPU_SYS_TRACE 0x47000000
+#define DRA7_MPU_SYS_TRACE_END 0x47FFFFFF
+#define DRA7_L4_PER1 0x48000000
+#define DRA7_L4_PER1_END 0x481FFFFF
+#define DRA7_MPU_PRM_BASE 0x48243000
+#define DRA7_MPU_PRM_BASE_END 0x48243FFF
+#define DRA7_WKUPGEN_BASE 0x48281000
+#define DRA7_WKUPGEN_BASE_END 0x48281FFF
+#define DRA7_MPU_CMU 0x48290000
+#define DRA7_MPU_CMU_END 0x4829FFFF
+#define DRA7_MPU_AXI2OCP 0x482A0000
+#define DRA7_MPU_AXI2OCP_END 0x482AEFFF
+#define DRA7_MPU_MA 0x482AF000
+#define DRA7_MPU_MA_END 0x482AFFFF
+#define DRA7_L4_PER2 0x48400000
+#define DRA7_L4_PER2_END 0x487FFFFF
+#define DRA7_L4_PER3 0x48800000
+#define DRA7_L4_PER3_END 0x48FFFFFF
+#define DRA7_OCMC_RAM2_CBUF 0x49000000
+#define DRA7_OCMC_RAM2_CBUF_END 0x497FFFFF
+#define DRA7_OCMC_RAM3_CBUF 0x49800000
+#define DRA7_OCMC_RAM3_CBUF_END 0x49FFFFFF
+#define DRA7_L4_CFG 0x4A000000
+#define DRA7_L4_CFG_END 0x4ADFFFFF
+#define DRA7_L4_WKUP 0x4AE00000
+#define DRA7_L4_WKUP_END 0x4AFFFFFF
+#define DRA7_QSPI_0_SPACE 0x4B300000
+#define DRA7_QSPI_0_SPACE_END 0x4B3FFFFF
+#define DRA7_EMIF1_CONFIG 0x4C000000
+#define DRA7_EMIF1_CONFIG_END 0x4CFFFFFF
+#define DRA7_EMIF2_CONFIG 0x4D000000
+#define DRA7_EMIF2_CONFIG_END 0x4DFFFFFF
+#define DRA7_DMM_CONFIG 0x4E000000
+#define DRA7_DMM_CONFIG_END 0x4FFFFFFF
+#define DRA7_GPMC_CONFIG 0x50000000
+#define DRA7_GPMC_CONFIG_END 0x50FFFFFF
+#define DRA7_PCIE_SS1 0x51000000
+#define DRA7_PCIE_SS1_END 0x517FFFFF
+#define DRA7_PCIE_SS2 0x51800000
+#define DRA7_PCIE_SS2_END 0x51FFFFFF
+#define DRA7_L3_INSTR 0x54000000
+#define DRA7_L3_INSTR_END 0x547FFFFF
+#define DRA7_DEBUGSS 0x54800000
+#define DRA7_DEBUGSS_END 0x54FFFFFF
+#define DRA7_IPU2_TARGET 0x55000000
+#define DRA7_IPU2_TARGET_END 0x557FFFFF
+#define DRA7_GPU_3D_DOMAIN 0x56000000
+#define DRA7_GPU_3D_DOMAIN_END 0x57FFFFFF
+#define DRA7_DSS_DOMAIN 0x58000000
+#define DRA7_DSS_DOMAIN_END 0x587FFFFF
+#define DRA7_BB2D 0x59000000
+#define DRA7_BB2D_END 0x59FFFFFF
+#define DRA7_IVA_CONFIG_DOMAIN 0x5A000000
+#define DRA7_IVA_CONFIG_DOMAIN_END 0x5A3FFFFF
+#define DRA7_IVA_SL2IF_DOMAIN 0x5B000000
+#define DRA7_IVA_SL2IF_DOMAIN_END 0x5B3FFFFF
+#define DRA7_QSPI_1_SPACE 0x5C000000
+#define DRA7_QSPI_1_SPACE_END 0x5FFFFFFF
+#define DRA7_SDRAM_DMM 0x60000000
+#define DRA7_SDRAM_DMM_END 0x7FFFFFFF
+
+
+#define DRA7_AUX_CORE_BOOT_0_OFFSET 0x800
+#define DRA7_AUX_CORE_BOOT_1_OFFSET 0x804
+
+#define DRA7_L3_PRM_MPU 0x48243000
+#define DRA7_L3_PRM_MPU_S 0x1000
+
+#define DRA7_L4CFG_TP_CM_CORE_AON_TARG 0x4A004000
+#define DRA7_L4CFG_TP_CM_CORE_AON_TARG_S 0x1000
+
+#define DRA7_L3_WKUGEN_MPU 0x48281000
+#define DRA7_L3_WKUGEN_MPU_S 0x1000
+
+#define DRA7_L4CFG_TP_CM_CORE_TARG 0x4a008000
+#define DRA7_L4CFG_TP_CM_CORE_TARG_S 0x2000
+
+#define DRA7_L4WKUP_TP_PRM_TARG 0x4AE06000
+#define DRA7_L4WKUP_TP_PRM_TARG_S 0x3000
+
+#define DRA7_L4WKUP_TP_SCRM_TARG 0x4AE0A000
+#define DRA7_L4WKUP_TP_SCRM_TARG_S 0x1000
+
+#define DRA7_L3_UART3 0x48020000
+#define DRA7_L3_UART3_S 0x1000
+
+#define DRA7_L3_UART1 0x4806A000
+#define DRA7_L3_UART1_S 0x1000
+
+#define REALTIME_COUNTER_BASE 0x48243200
+#define INCREMENTER_NUMERATOR_OFFSET 0x10
+#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
+#define NUMERATOR_DENUMERATOR_MASK 0xfffff000
+#define PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD 0x00010000
+
+#define DRA7_CKGEN_PRM_BASE DRA7_L4WKUP_TP_PRM_TARG + 0x100
+#define DRA7_CM_CLKSEL_SYS 0x10
+#define SYS_CLKSEL_MASK 0xfffffff8
+
+
+#endif /* __ASM_ARM_PLATFORMS_DRA7XX_H */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
--
1.7.9.5
_______________________________________________
Xen-devel mailing list
Xen-devel@xxxxxxxxxxxxx
http://lists.xen.org/xen-devel
|
 |
Lists.xenproject.org is hosted with RackSpace, monitoring our |