Re: [Xen-devel] [PATCH 0/2] vgic emulation and GICD_ITARGETSR

[Ian Campbell <Ian.Campbell@xxxxxxxxxx>]

On Sun, 2014-05-25 at 19:06 +0100, Stefano Stabellini wrote:
> Hi all,
> this small patch series improves vgic emulation in relation to
> GICD_ITARGETSR and irq delivery.
> 
> At the moment we don't support irq delivery to vcpu != 0, so prevent the
> guest from setting itarget to something != 0.

How hard would this be to support? I think all interrupts already all
arrive at pCPU==0, so we must be capable of forwarding them to whichever
pCPU might be running vCPU==0? Is extending that to select wihch vcpu to
send to hard?

> vgic_enable_irqs and vgic_disable_irqs currently ignore the itarget
> settings and just enable/disable irqs on the current vcpu. Fix their
> behaviour to enable/disable irqs on the vcpu set by itarget, that is
> always vcpu0 for irq >= 32.
> 
> 
> Stefano Stabellini (2):
>       xen/arm: add a warning if the guest asks for SPI delivery to vcpu != 0.
>       xen/arm: observe itarget setting in vgic_enable_irqs and 
> vgic_disable_irqs
> 
>  xen/arch/arm/vgic.c |   47 +++++++++++++++++++++++++++++++++++++++--------
>  1 file changed, 39 insertions(+), 8 deletions(-)



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