Re: [Xen-devel] undefined instruction error during HYP mode switch for arndale-octa board

[HyonYoung Choi <commani@xxxxxxxxx>]

Hello Julien,

At first, I want to know who is the maintainer for this U-Boot or Hypervisor mode support section.

From previous email, I found that U-boot is running already in non-secure mode.

From the comment of the erroneous code in arch/arm/cpu/armv7/nonsec_vert.S,Â

it is guessed that it tries to switch non-secure mode assuming the CPU is in secure mode.

========================================

/*

Â* Switch a core to non-secure state.

Â*

Â* Â1. initialize the GIC per-core interface

Â* Â2. allow coprocessor access in non-secure modes

Â* Â3. switch the cpu mode (by calling "smc #0")

Â*

Â* Called from smp_pen by secondary cores and directly by the BSP.

Â* Do not assume that the stack is available and only use registers

Â* r0-r3 and r12.

Â*

Â* PERIPHBASE is used to get the GIC address. This could be 40 bits long,

Â* though, but we check this in C before calling this function.

Â*/

ENTRY(_nonsec_init)

=========================================

But I have known CPU is already in non-secure mode,Â

so, we commented out the calling _nonsec_init() and

just call hypervisor mode switch function only as below:

=========================================

static void do_nonsec_virt_switch(void)

{

#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)

// Â Â Âif (armv7_switch_nonsec() == 0)

#ifdef CONFIG_ARMV7_VIRT

        if (armv7_switch_hyp() == 0)

            debug("entered HYP mode\n");

#else

        debug("entered non-secure state\n");

#endif

#endif

}

=========================================

The code of function armv7_switch_hyp() is simple:

=========================================

ENTRY(_switch_to_hyp)

    mov   r0, lr

    mov   r1, sp             Â@ save SVC copy of LR and SP

    isb

    hvc #0          @ for older asm: .byte 0x70, 0x00, 0x40, 0xe1

    mov   sp, r1

    mov   lr, r0             Â@ restore SVC copy of LR and SP

    bx   Âlr

ENDPROC(_switch_to_hyp)

===========================================

But it hangs while booting in "hvc #0" instruction.

----------------------------------------------------------------------

## Booting kernel from Legacy Image at 20007000 ...

 ÂImage Name: ÂÂ

 ÂImage Type:  ARM Linux Kernel Image (uncompressed)

 ÂData Size:  Â656144 Bytes = 640.8 KiB

 ÂLoad Address: 20008000

 ÂEntry Point: Â20008000

 ÂVerifying Checksum ... OK

## Flattened Device Tree blob at 21f00000

 ÂBooting using the fdt blob at 0x21f00000

 ÂLoading Kernel Image ... OK

OK

 Âreserving fdt memory region: addr=21f00000 size=8000

 ÂUsing Device Tree in place at 21f00000, end 21f0afff

 switch_hyp: CPU supports virt ext

----------------------------------------------------------------------

From the original sequence of function calls,

nonsec_init() is for turning to non-secure mode,

then it calls switch_to_hyp () in non-secure mode.

Is there any preparation for executing "hvc" instruction or any privilege to be executed?

Best,

Hyonyoung

2014-04-21 8:39 GMT-04:00 Julien Grall <julien.grall@xxxxxxxxxx>:

Hello HyonYoung,

On 18/04/14 22:26, HyonYoung Choi wrote:

I am trying to port xen to arndale-octa board.

I am using u-boot modified for arndale-octa
from tracking-arndale_octa branch of
http://landing-teams/working/samsung/u-boot.git

Because there is no HYP mode switch code in the u-boot,
I tried to port your code in
http://git.linaro.org/git/people/andre.przywara/u-boot.git.
I also put debug code.

In booting, it reboot infinitely with following error message:
======================
  switch_hyp: GIC dist enabled
 Âswitch_hyp: 224 interrupts supportd
 Âswitch_hyp: all interrupts switched to non-secure
 Âswitch_hyp: setting SP start start address (0x9f86d6b4)
 Âswitch_hyp: kicked all CPUs
 ÂVBAR before: 0x9f86c000
undefined instruction
pc : [<9f86d748>] Â Â Â Â Âlr : [<9f86d600>]
sp : 9f7638c0 Âip : 0000000f   fp : 9f86e4b4
r10: 9f8ad294 Âr9 : 00000000 Â Â r8 : 9f763f10
r7 : 00000000 Âr6 : ffffffff   r5 : 00000007 Âr4 : 9f86c000
r3 : 10482000 Âr2 : 10480000 Â Â r1 : 016e3600 Âr0 : 00010000
Flags: nZCv ÂIRQs off ÂFIQs off ÂMode SVC_32
Resetting CPU ...
========================

The problematic code is "mcr   p15, 0, r1, c1, c1, 2"
in arch/arm/cpu/armv7/nonsec_virt.S , nonsec_init function
Do you have any idea about this error?

U-boot is trying to write into NSCAR. This register is only writeable in Secure PL1 mode.

I suspect U-boot is running in non-secure mode. You may have the same problem as the odroid-xu where the SPL BL2 code brings up CPU in NS mode (see http://www.gossamer-threads.com/lists/xen/devel/325364#325364).

Regards,

--
Julien Grall

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