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Re: [Xen-devel] [PATCH 2/4] arm: add a function to invoke the PSCI handler and use it



On 11/26/2013 12:18 PM, Ian Campbell wrote:
On Mon, 2013-11-25 at 13:02 +0100, Andre Przywara wrote:
The PSCI handler is invoked via a secure monitor call with the
arguments defined in registers [1]. Copy the function from the
Linux code and adjust it to work on both ARM32 and ARM64.
Later use that function instead of the generic GIC SEV kick to
actually bring up the secondary CPUs.

[1]: 
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0022b/index.html

Signed-off-by: Andre Przywara <andre.przywara@xxxxxxxxxx>
---
  xen/arch/arm/arm32/smpboot.c |  1 -
  xen/arch/arm/smpboot.c       | 39 +++++++++++++++++++++++++++++++++++----
  2 files changed, 35 insertions(+), 5 deletions(-)

diff --git a/xen/arch/arm/arm32/smpboot.c b/xen/arch/arm/arm32/smpboot.c
index 88fe8fb..fcf653f 100644
--- a/xen/arch/arm/arm32/smpboot.c
+++ b/xen/arch/arm/arm32/smpboot.c
@@ -10,7 +10,6 @@ int __init arch_smp_init(void)

  int __init arch_cpu_init(int cpu, struct dt_device_node *dn)
  {
-    /* TODO handle PSCI init */
      return 0;
  }

diff --git a/xen/arch/arm/smpboot.c b/xen/arch/arm/smpboot.c
index 97bd414..44326d8 100644
--- a/xen/arch/arm/smpboot.c
+++ b/xen/arch/arm/smpboot.c
@@ -89,6 +89,29 @@ smp_clear_cpu_maps (void)
      cpu_logical_map(0) = READ_SYSREG(MPIDR_EL1) & MPIDR_HWID_MASK;
  }

+#ifdef CONFIG_ARM_32
+#define REG_PREFIX "r"
+#else
+#define REG_PREFIX "x"
+#endif
+
+static noinline int __invoke_psci_fn_smc(u32 function_id, u32 arg0, u32 arg1,
+                                         u32 arg2)

Please can you put this in psci.c and provide wrappers e.g.
psci_cpu_up(). THese can return some suitable errno if PSCI isn't
enabled. Or we could add a psci_enabled() call

Why noinline?

This was copied from Linux and I thought it was there for a reason, so I kept it. But looking closer this was to make sure Linux can use function pointers later (to abstract hvc and smc calling), so we can remove this for Xen.

Regards,
Andre.


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