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Re: [Xen-devel] ARM GIC Security Extensions and Xen

On 10/28/2013 04:29 AM, Mj Embd wrote:
Slight modification GICC_AIAR (%s/GICV/GICC/g)

On Mon, Oct 28, 2013 at 4:57 PM, Mj Embd <mj.embd@xxxxxxxxx> wrote:
Does Xen GIC implementation use Grp0 as secure and Grp 1 as NS as
mentioned  in GIC 400 manual
When a GIC that implements the GIC Security Extensions is connected to
a processor that implements the ARM Security Extensions:

Group 0 interrupts are Secure interrupts, and Group 1 interrupts are
Non-secure interrupts.

ARM IHI 0048B.b Non-Confidential ID072613 Pg 1-16

The manual also states

In GICv2, ARM recommends that separate registers are used to manage
Group 0 and Group 1 interrupts:

GICV_IAR, GICV_EOIR, and GICV_HPPIR for Group 0 interrupts GICV_AIAR,
GICV_AEOIR, and GICV_AHPPIR for Group 1 interrupts.

pg 5-162

I was not able to find GICV_AIAR being used in code.

Xen is running in non-secure mode. The register GICC_AIAR is only used for secure mode. Actually in secure mode, it's an alias to GICC_IAR.

Julien Grall

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