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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCH v4 3/4] VMX: use proper instruction mnemonics if assembler supports them
>>> On 26.08.13 at 16:18, Andrew Cooper <andrew.cooper3@xxxxxxxxxx> wrote:
> On 26/08/2013 15:03, Jan Beulich wrote:
>> + asm volatile (
>> +#ifdef HAVE_GAS_VMX
>> + "vmread %2, %1\n\t"
>> +#else
>> + VMREAD_OPCODE MODRM_EAX_ECX
>> +#endif
>> + /* CF==1 or ZF==1 --> rc = 0 */
>> + "setnbe %0"
>> +#ifdef HAVE_GAS_VMX
>> + : "=qm" (okay), "=rm" (*value)
>> + : "r" (field)
>> +#else
>> + : "=qm" (okay), "=c" (*value)
>> + : "a" (field)
>> +#endif
>
> From what I can work out while googling, the q constraint is equivalent
> to the r constraint for 64bit code.
>
> For consistency sake, I would suggest "=rm" (okay) here
And I'd like to keep it the way it is for generality's sake (i.e. not
making the code more 32-bit unclean than we need to).
>> @@ -365,14 +398,22 @@ static inline void __invept(int type, u6
>> !cpu_has_vmx_ept_invept_single_context )
>> type = INVEPT_ALL_CONTEXT;
>>
>> - asm volatile ( INVEPT_OPCODE
>> - MODRM_EAX_08
>> + asm volatile (
>> +#ifdef HAVE_GAS_EPT
>> + "invept %0, %q1\n"
>
> Another stray q
No - operand 1 is of type "int", and while the high 32 bits get
ignored (i.e. we don't need to do any zero- or sign-extension), we
still need to specify the 64-bit register name here. Or wait - I
thought it would ignore the upper bits, but it's not documented to.
In which case this involves more than just dropping the q modifier.
>> @@ -385,7 +426,12 @@ static inline void __invvpid(int type, u
>> } __attribute__ ((packed)) operand = {vpid, 0, gva};
>>
>> /* Fix up #UD exceptions which occur when TLBs are flushed before
>> VMXON. */
>> - asm volatile ( "1: " INVVPID_OPCODE MODRM_EAX_08
>> + asm volatile ( "1: "
>> +#ifdef HAVE_GAS_EPT
>> + "invvpid %0, %q1\n"
>
> And another
Same here.
Jan
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