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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] xen: arm: beginning the removal of mode_switch.S
I did some hacking on boot-wrapper.git on the train to debconf and made it support building a zImage container encapsulating Xen+Linux+initramfs +fdt. Xen is optional so it can be used to boot natively too. You can find the code in the multiplatform branch of http://xenbits.xen.org/gitweb/?p=people/ianc/boot-wrapper.git It has build time (Kconfig driven) options to support: * cubieboard2 (boots native ok, weird issue under Xen) * arndale (code taken from existing mode switch.S, untested) * vexpress and fastmodel (untested) The code is pretty hacked up from the original (which only really supported fastmodels, and had limited configurability) and it could certainly be structured to be quite a bit cleaner (plus I think I got a bit carried away with using Kconfig for everything). I'd rather have some skanky hacked up code here than in Xen though, so I think this is an acceptable level of hackedupness. At the moment it is sufficient to allow us to do away with the enter_hyp_mode bits and the clock frequency, gic setup etc, along the lines of the patch below. It doesn't yet allow us to get rid of the kick_cpus stuff. My plan for platforms which don't do the right thing here would be to add a mechanism to use dtb /memreserve/ (and teach Xen about that construct) to carve out a little bit of memory which secondary CPUs could safely be left spinning in. The platform code would expose its normal interface (e.g. SYS_FLAGS on vexpress and fastmodel), eventually maybe we'd do PSCI too (which might let us skip reserving some memory since 2ndary cpus would be in secure mode and could use the special ram regions reserved for that) I might have time for this on the train on the way home, but since my cubieboard2 can't do SMP yet (even on native Linux, bringup looks complex) I suppose that means I need to test and debug the fastmodel support first... As we add new platforms I think we should first push back on the vendors to fix their firmware but when that turns out to not be possible we should move to patching this code with platform hacks instead of adding more stuff to mode_switch.S, IMO the only blocker to this is the kick_cpu support. What does everyone think? 8<------------ commit 487c0de6b1d541a9706ebd18c12e3981328a32af Author: Ian Campbell <ian.campbell@xxxxxxxxxx> Date: Tue Aug 13 18:20:21 2013 +0100 xen: arm: Remove enter_hyp_mode from mode_switch.S bootwrapper.git can cope with this on both the platforms included here. mode_switch.S isn't quite dead yet -- need to handle kick_cpus. Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx> diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 1c9bdaf..1b75f65 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -168,10 +168,10 @@ boot_cpu: b fail 1: /* OK, we're in Secure state. */ - PRINT("- Started in Secure state -\r\n- Entering Hyp mode -\r\n") - ldr r0, =enter_hyp_mode /* VA of function */ - adr lr, hyp /* Set return address for call */ - add pc, r0, r10 /* Call PA of function */ + PRINT("- Started in Secure state -\r\n" \ + "- Xen must be entered in Hyp mode -\r\n" \ + "- Try using bootwrapper? -\r\n") + b fail hyp: diff --git a/xen/arch/arm/arm32/mode_switch.S b/xen/arch/arm/arm32/mode_switch.S index 3500eb0..89e80f1 100644 --- a/xen/arch/arm/arm32/mode_switch.S +++ b/xen/arch/arm/arm32/mode_switch.S @@ -68,91 +68,6 @@ kick_cpus_sgi: mov pc, lr -/* Get up a CPU into Hyp mode. Clobbers r0-r3. - * - * r5: Machine ID - * r12: CPU number - * - * This code is specific to the VE model/Arndale, and not intended to be used - * on production systems. As such it's a bit hackier than the main - * boot code in head.S. In future it will be replaced by better - * integration with the bootloader/firmware so that Xen always starts - * in Hyp mode. - * Clobber r0 - r4 */ - -.globl enter_hyp_mode -enter_hyp_mode: - mov r3, lr /* Put return address in non-banked reg */ - cpsid aif, #0x16 /* Enter Monitor mode */ - mrc CP32(r0, SCR) - orr r0, r0, #0x100 /* Set HCE */ - orr r0, r0, #0xb1 /* Set SCD, AW, FW and NS */ - bic r0, r0, #0xe /* Clear EA, FIQ and IRQ */ - mcr CP32(r0, SCR) - - ldr r2, =MACH_TYPE_SMDK5250 /* r4 := Arndale machine ID */ - /* By default load Arndale defaults values */ - ldr r0, =EXYNOS5_TIMER_FREQUENCY /* r0 := timer's frequency */ - ldr r1, =EXYNOS5_GIC_BASE_ADDRESS /* r1 := GIC base address */ - /* If it's not the Arndale machine ID, load VE values */ - teq r5, r2 - ldrne r0, =V2M_TIMER_FREQUENCY - ldrne r1, =V2M_GIC_BASE_ADDRESS - - /* Ugly: the system timer's frequency register is only - * programmable in Secure state. Since we don't know where its - * memory-mapped control registers live, we can't find out the - * right frequency. */ - mcr CP32(r0, CNTFRQ) - - mrc CP32(r0,NSACR) - ldr r4, =0x3fff /* Allow access to all co-processors in NS mode */ - orr r0, r0, r4 - orr r0, r0, #(1<<18) /* CA7/CA15: Allow access to ACTLR.SMP in NS mode */ - mcr CP32(r0, NSACR) - - add r0, r1, #GIC_DR_OFFSET - /* Disable the GIC distributor, on the boot CPU only */ - mov r4, #0 - teq r12, #0 /* Is this the boot CPU? */ - streq r4, [r0] - /* Continuing ugliness: Set up the GIC so NS state owns interrupts, - * The first 32 interrupts (SGIs & PPIs) must be configured on all - * CPUs while the remainder are SPIs and only need to be done one, on - * the boot CPU. */ - add r0, r0, #0x80 /* GICD_IGROUP0 */ - mov r2, #0xffffffff /* All interrupts to group 1 */ - str r2, [r0] /* Interrupts 0-31 (SGI & PPI) */ - teq r12, #0 /* Boot CPU? */ - bne skip_spis /* Don't route SPIs on secondary CPUs */ - - add r4, r1, #GIC_DR_OFFSET - ldr r4, [r4, #4] /* r4 := Interrupt Controller Type Reg */ - and r4, r4, #GICD_TYPE_LINES /* r4 := number of SPIs */ -1: teq r4, #0 - beq skip_spis - add r0, r0, #4 /* Go to the new group */ - str r2, [r0] /* Update the group */ - sub r4, r4, #1 - b 1b -skip_spis: - /* Disable the GIC CPU interface on all processors */ - add r0, r1, #GIC_CR_OFFSET - mov r1, #0 - str r1, [r0] - /* Must drop priority mask below 0x80 before entering NS state */ - ldr r1, =0xff - str r1, [r0, #0x4] /* -> GICC_PMR */ - /* Reset a few config registers */ - mov r0, #0 - mcr CP32(r0, FCSEIDR) - mcr CP32(r0, CONTEXTIDR) - - mrs r0, cpsr /* Copy the CPSR */ - add r0, r0, #0x4 /* 0x16 (Monitor) -> 0x1a (Hyp) */ - msr spsr_cxsf, r0 /* into the SPSR */ - movs pc, r3 /* Exception-return into Hyp mode */ - /* * Local variables: * mode: ASM diff --git a/xen/include/asm-arm/platforms/exynos5.h b/xen/include/asm-arm/platforms/exynos5.h index ee5bdfa..4c414b3 100644 --- a/xen/include/asm-arm/platforms/exynos5.h +++ b/xen/include/asm-arm/platforms/exynos5.h @@ -20,9 +20,6 @@ /* GIC Base Address */ #define EXYNOS5_GIC_BASE_ADDRESS 0x10480000 -/* Timer's frequency */ -#define EXYNOS5_TIMER_FREQUENCY (24 * 1000 * 1000) /* 24 MHz */ - /* Arndale machine ID */ #define MACH_TYPE_SMDK5250 3774 diff --git a/xen/include/asm-arm/platforms/vexpress.h b/xen/include/asm-arm/platforms/vexpress.h index 982a293..1ffafee 100644 --- a/xen/include/asm-arm/platforms/vexpress.h +++ b/xen/include/asm-arm/platforms/vexpress.h @@ -38,9 +38,6 @@ int vexpress_syscfg(int write, int function, int device, uint32_t *data); /* GIC base address */ #define V2M_GIC_BASE_ADDRESS 0x2c000000 -/* Timer's frequency */ -#define V2M_TIMER_FREQUENCY 0x5f5e100 /* 100 Mhz */ - #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARM_PLATFORMS_VEXPRESS_H */ _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx http://lists.xen.org/xen-devel
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