--- a/xen/arch/x86/xstate.c
+++ b/xen/arch/x86/xstate.c
@@ -97,8 +97,25 @@ void xsave(struct vcpu *v, uint64_t mask
             asm volatile ( "fnstenv %0" : "=m" (fpu_env) );
             ptr->fpu_sse.fip.sel = fpu_env.fcs;
             ptr->fpu_sse.fdp.sel = fpu_env.fds;
+ if((!fpu_env.fcs && ptr->fpu_sse.fip.offs) ||
+    (!fpu_env.fds && ptr->fpu_sse.fdp.offs)) {//temp
+  static unsigned long count, thresh;
+  if(++count > thresh) {
+   thresh |= thresh + 1;
+   printk("d%dv%d: fip=%04x:%08x fdp=%04x:%08x\n", v->domain->domain_id, v->vcpu_id,
+          fpu_env.fcs, ptr->fpu_sse.fip.offs, fpu_env.fds, ptr->fpu_sse.fdp.offs);
+  }
+ }
             word_size = 4;
         }
+ else if(word_size >= 0 && is_hvm_vcpu(v) && hvm_guest_x86_mode(v) < 8) {//temp
+  static unsigned long count, thresh;
+  if(++count > thresh) {
+   thresh |= thresh + 1;
+   printk("d%dv%d: fip=%"PRIx64" fdp=%"PRIx64" w=%d\n", v->domain->domain_id, v->vcpu_id,
+          ptr->fpu_sse.fip.addr, ptr->fpu_sse.fdp.addr, word_size);
+  }
+ }
     }
     else
     {
@@ -110,6 +127,16 @@ void xsave(struct vcpu *v, uint64_t mask
             asm volatile ( ".byte 0x0f,0xae,0x27"
                            : "=m" (*ptr)
                            : "a" (lmask), "d" (hmask), "D" (ptr) );
+ if((!ptr->fpu_sse.fip.sel && ptr->fpu_sse.fip.offs) ||
+    (!ptr->fpu_sse.fdp.sel && ptr->fpu_sse.fdp.offs)) {//temp
+  static unsigned long count, thresh;
+  if(++count > thresh) {
+   thresh |= thresh + 1;
+   printk("d%dv%d: FIP=%04x:%08x FDP=%04x:%08x\n", v->domain->domain_id, v->vcpu_id,
+          ptr->fpu_sse.fip.sel, ptr->fpu_sse.fip.offs,
+          ptr->fpu_sse.fdp.sel, ptr->fpu_sse.fdp.offs);
+  }
+ }
         word_size = 4;
     }
     if ( word_size >= 0 )
@@ -145,6 +172,14 @@ void xrstor(struct vcpu *v, uint64_t mas
     switch ( __builtin_expect(ptr->fpu_sse.x[FPU_WORD_SIZE_OFFSET], 8) )
     {
     default:
+ if(is_hvm_vcpu(v) && (ptr->fpu_sse.fip.addr | ptr->fpu_sse.fdp.addr)) {//temp
+  static unsigned long count, thresh;
+  if(++count > thresh) {
+   thresh |= thresh + 1;
+   printk("d%dv%d: FIP=%"PRIx64" FDP=%"PRIx64" w=%d\n", v->domain->domain_id, v->vcpu_id,
+          ptr->fpu_sse.fip.addr, ptr->fpu_sse.fdp.addr, ptr->fpu_sse.x[FPU_WORD_SIZE_OFFSET]);
+  }
+ }
         asm volatile ( "1: .byte 0x48,0x0f,0xae,0x2f\n"
                        ".section .fixup,\"ax\"      \n"
                        "2: mov %5,%%ecx             \n"