[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Xen-devel] [PATCH] xen: arm: correct vfp save/restore asm constraints.



On Wed, 2013-07-10 at 02:05 -0700, Julien Grall wrote:
> On Mon, Jul 8, 2013 at 7:19 AM, Ian Campbell <ian.campbell@xxxxxxxxxx> wrote:
> > Some versions of gcc complain:
> >> vfp.c: In function 'vfp_restore_state':
> >> vfp.c:45:27: error: memory input 0 is not directly addressable
> >> vfp.c:51:31: error: memory input 0 is not directly addressable
> >
> > There is no way to express the constraint we want (which is the address of 
> > the
> > array, clobbering the whole array). Therefore we have to fake it up by using
> > two constraints.
> >
> > Signed-off-by: Ian Campbell <ijc@xxxxxxxxxxxxxx>
> > Acked-by: Will.Deacon@xxxxxxx
> 
> Acked-by: Julien Grall <julien.grall@xxxxxxxxxx>

Thanks, I'd commit this ASAP since it has broken the push tests but
unfortunately I'm travelling and the ssh gateway I would need to use is
down. (which is also why this comes from my personal email).

If one of the other committers wants to throw this in in the meantime
then please do so.

Ian.

> 
> > ---
> >  xen/arch/arm/arm32/vfp.c | 17 +++++++++--------
> >  1 file changed, 9 insertions(+), 8 deletions(-)
> >
> > diff --git a/xen/arch/arm/arm32/vfp.c b/xen/arch/arm/arm32/vfp.c
> > index 6780131..0069acd 100644
> > --- a/xen/arch/arm/arm32/vfp.c
> > +++ b/xen/arch/arm/arm32/vfp.c
> > @@ -22,15 +22,15 @@ void vfp_save_state(struct vcpu *v)
> >      }
> >
> >      /* Save {d0-d15} */
> > -    asm volatile("stc p11, cr0, %0, #32*4"
> > -                 : "=Q" (v->arch.vfp.fpregs1));
> > +    asm volatile("stc p11, cr0, [%1], #32*4"
> > +                 : "=Q" (*v->arch.vfp.fpregs1) : "r" 
> > (v->arch.vfp.fpregs1));
> >
> >      /* 32 x 64 bits registers? */
> >      if ( (READ_CP32(MVFR0) & MVFR0_A_SIMD_MASK) == 2 )
> >      {
> >          /* Save {d16-d31} */
> > -        asm volatile("stcl p11, cr0, %0, #32*4"
> > -                     : "=Q" (v->arch.vfp.fpregs2));
> > +        asm volatile("stcl p11, cr0, [%1], #32*4"
> > +                     : "=Q" (*v->arch.vfp.fpregs2) : "r" 
> > (v->arch.vfp.fpregs2));
> >      }
> >
> >      WRITE_CP32(v->arch.vfp.fpexc & ~(FPEXC_EN), FPEXC);
> > @@ -38,17 +38,18 @@ void vfp_save_state(struct vcpu *v)
> >
> >  void vfp_restore_state(struct vcpu *v)
> >  {
> > +    //uint64_t test[16];
> >      WRITE_CP32(READ_CP32(FPEXC) | FPEXC_EN, FPEXC);
> >
> >      /* Restore {d0-d15} */
> > -    asm volatile("ldc p11, cr0, %0, #32*4"
> > -                 : : "Q" (v->arch.vfp.fpregs1));
> > +    asm volatile("ldc p11, cr0, [%1], #32*4"
> > +                 : : "Q" (*v->arch.vfp.fpregs1), "r" 
> > (v->arch.vfp.fpregs1));
> >
> >      /* 32 x 64 bits registers? */
> >      if ( (READ_CP32(MVFR0) & MVFR0_A_SIMD_MASK) == 2 ) /* 32 x 64 bits 
> > registers */
> >          /* Restore {d16-d31} */
> > -        asm volatile("ldcl p11, cr0, %0, #32*4"
> > -                     : : "Q" (v->arch.vfp.fpregs2));
> > +        asm volatile("ldcl p11, cr0, [%1], #32*4"
> > +                     : : "Q" (*v->arch.vfp.fpregs2), "r" 
> > (v->arch.vfp.fpregs2));
> >
> >      if ( v->arch.vfp.fpexc & FPEXC_EX )
> >      {
> > --
> > 1.8.3.2
> >
> >
> > _______________________________________________
> > Xen-devel mailing list
> > Xen-devel@xxxxxxxxxxxxx
> > http://lists.xen.org/xen-devel



_______________________________________________
Xen-devel mailing list
Xen-devel@xxxxxxxxxxxxx
http://lists.xen.org/xen-devel


 


Rackspace

Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.