Re: [Xen-devel] Unable to retrieve IRQ 1 from the device tree on OMAP5432

[Ian Campbell <Ian.Campbell@xxxxxxxxxx>]

On Wed, 2013-07-03 at 21:40 +0800, Chen Baozi wrote:
> Hi Ian & Julien,
> 
> After hacking the ns16550 driver on ARM, I can get the console output now
> on OMAP5432 platform. However, when coming to the point of init_xen_time(),
> I came across another problem:
> 
> (XEN) ****************************************
> (XEN) Panic on CPU 0:
> (XEN) Timer: Unable to retrieve IRQ 1 from the device tree
> (XEN) ****************************************
> (XEN)
> (XEN) Reboot in five seconds...
> 
> And its code path is:
> 
> - start_xen()
>  - init_xen_time()
>   - dt_device_get_irq()
>    - dt_device_get_raw_irq()
> 
> where it failed when judging the following condition:
> 
> 01    /* Check index */
> 02    if ( (index + 1) * intsize > intlen )
> 03        goto out;
> 
> while "index = TIMER_PHYS_NONSECURE_PPI", "intsize = 3" and "intlen = 3".
> 
> If I enable "DEBUG_DT", I can get the following debug info:
> 
> (XEN) dt_device_get_raw_irq: dev=/cpus/cpu@0/timer, index=0
> (XEN)  intspec=1 intlen=3
> (XEN)  intsize=3 intlen=3
> (XEN) dt_irq_map_raw: 
> par=/ocp/interrupt-controller@48211000,intspec=[0x00000001 
> 0x0000000e...],ointsize=3
> (XEN) dt_irq_map_raw: ipar=/ocp/interrupt-controller@48211000, size=3
> (XEN)  -> addrsize=1
> (XEN)  -> got it !
> (XEN) dt_device_get_raw_irq: dev=/cpus/cpu@0/timer, index=1
> (XEN)  intspec=1 intlen=3
> (XEN)  intsize=3 intlen=3
> 
> And the related dts writes:
> 
>        cpus {
>                cpu@0 {
>                        compatible = "arm,cortex-a15";
>                        timer {
>                                compatible = "arm,armv7-timer";
>                                /* 14th PPI IRQ, active low level-sensitive */
>                                interrupts = <1 14 0x308>;

You don't have enough interrupts here. Compare with the vexpress dts:
        timer {
                compatible = "arm,armv7-timer";
                interrupts = <1 13 0xf08>,
                             <1 14 0xf08>,
                             <1 11 0xf08>,
                             <1 10 0xf08>;
        };

These cover the virt and hyperviso timers as well as the secure and
non-secure physical timers.

Most platforms seem to have the timer node at the top-level rather than
duplicated for each cpu node.

>                                clock-frequency = <6144000>;
>                        };                                                     
>          
>                };
>                cpu@1 {
>                        compatible = "arm,cortex-a15";
>                        timer {
>                                compatible = "arm,armv7-timer";
>                                /* 14th PPI IRQ, active low level-sensitive */
>                                interrupts = <1 14 0x308>;
>                                clock-frequency = <6144000>;
>                        };
>                };
>        };
> 
> Just couldn't understand "(index + 1) * intsize > intlen" stands for, and
> wondering when it would be always satisifed while "index" is increasing from 0
> to 3 and "intlen" is the length of interrupts property which is "3" on
> both OMAP5 and EXYNOS5.
> 
> Any ideas?
> 
> Cheers,
> 
> Baozi



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