Re: [Xen-devel] [PATCH 2 of 2] AMD/iommu: SR56x0 Erratum 64 - Reset all head & tail pointers

["Suthikulpanit, Suravee" <Suravee.Suthikulpanit@xxxxxxx>]

Acked: Suravee Suthikulpanit <suravee.suthikulpanit@xxxxxxx>

Thank you,

Suravee

-----Original Message-----
From: Andrew Cooper [mailto:andrew.cooper3@xxxxxxxxxx] 
Sent: Wednesday, May 22, 2013 5:14 AM
To: xen-devel@xxxxxxxxxxxxx
Cc: Keir Fraser; Jan Beulich; Suthikulpanit, Suravee; Shin, Jacob
Subject: [PATCH 2 of 2] AMD/iommu: SR56x0 Erratum 64 - Reset all head & tail 
pointers

Reference at time of patch:
http://support.amd.com/us/ChipsetMotherboard_TechDocs/46303.pdf

Erratum 64 states that the head and tail pointers for the Command buffer and 
Event log are only reset on a cold boot, not a warm boot.

While the erratum is limited to systems using SR56xx chipsets (such as Family 
10h CPUs), resetting the pointers is a sensible action in all cases, including 
the PPR log for consistency.

Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>

--

Changes since v1:
 * Reset PPR head/tail pointer as well
 * Make use of writeq()

diff -r 12e991b1d50b -r 50eb8a3229ec xen/drivers/passthrough/amd/iommu_init.c
--- a/xen/drivers/passthrough/amd/iommu_init.c
+++ b/xen/drivers/passthrough/amd/iommu_init.c
@@ -154,6 +154,11 @@ static void register_iommu_cmd_buffer_in
                          IOMMU_CMD_BUFFER_LENGTH_MASK,
                          IOMMU_CMD_BUFFER_LENGTH_SHIFT, &entry);
     writel(entry, iommu->mmio_base+IOMMU_CMD_BUFFER_BASE_HIGH_OFFSET);
+
+    /* Reset head/tail pointer. SR56x0 Erratum 64 means this might not happen
+     * automatically for us. */
+    writeq(0, iommu->mmio_base + IOMMU_CMD_BUFFER_HEAD_OFFSET);
+    writeq(0, iommu->mmio_base + IOMMU_CMD_BUFFER_TAIL_OFFSET);
 }
 
 static void register_iommu_event_log_in_mmio_space(struct amd_iommu *iommu) @@ 
-182,6 +187,11 @@ static void register_iommu_event_log_in_
                         IOMMU_EVENT_LOG_LENGTH_MASK,
                         IOMMU_EVENT_LOG_LENGTH_SHIFT, &entry);
     writel(entry, iommu->mmio_base+IOMMU_EVENT_LOG_BASE_HIGH_OFFSET);
+
+    /* Reset head/tail pointer. SR56x0 Erratum 64 means this might not happen
+     * automatically for us. */
+    writeq(0, iommu->mmio_base + IOMMU_EVENT_LOG_HEAD_OFFSET);
+    writeq(0, iommu->mmio_base + IOMMU_EVENT_LOG_TAIL_OFFSET);
 }
 
 static void register_iommu_ppr_log_in_mmio_space(struct amd_iommu *iommu) @@ 
-210,6 +220,9 @@ static void register_iommu_ppr_log_in_mm
                         IOMMU_PPR_LOG_LENGTH_MASK,
                         IOMMU_PPR_LOG_LENGTH_SHIFT, &entry);
     writel(entry, iommu->mmio_base + IOMMU_PPR_LOG_BASE_HIGH_OFFSET);
+
+    writeq(0, iommu->mmio_base + IOMMU_PPR_LOG_HEAD_OFFSET);
+    writeq(0, iommu->mmio_base + IOMMU_PPR_LOG_TAIL_OFFSET);
 }
 
 



_______________________________________________
Xen-devel mailing list
Xen-devel@xxxxxxxxxxxxx
http://lists.xen.org/xen-devel