[Xen-devel] [RFC 26/29] xen/arm: Add Exynos 4210 UART support for early printk

[Julien Grall <julien.grall@xxxxxxxxxx>]

Signed-off-by: Julien Grall <julien.grall@xxxxxxxxxx>
---
 config/arm32.mk                    |    1 +
 xen/arch/arm/Rules.mk              |    4 ++
 xen/arch/arm/arm32/Makefile        |    1 +
 xen/arch/arm/arm32/debug-exynos5.S |   81 ++++++++++++++++++++++++++++++++++++
 4 files changed, 87 insertions(+)
 create mode 100644 xen/arch/arm/arm32/debug-exynos5.S

diff --git a/config/arm32.mk b/config/arm32.mk
index 593a1d1..01c1490 100644
--- a/config/arm32.mk
+++ b/config/arm32.mk
@@ -17,6 +17,7 @@ CFLAGS += -marm
 # Possible value:
 #   - none: no early printk
 #   - pl011: printk with PL011 UART
+#   - exynos5: printk with the second exynos 5 UART
 CONFIG_EARLY_PRINTK := none
 HAS_PL011 := y
 HAS_EXYNOS5 := y
diff --git a/xen/arch/arm/Rules.mk b/xen/arch/arm/Rules.mk
index 2053b1e..7dcc0b7 100644
--- a/xen/arch/arm/Rules.mk
+++ b/xen/arch/arm/Rules.mk
@@ -43,5 +43,9 @@ ifeq ($(CONFIG_EARLY_PRINTK), pl011)
 EARLY_PRINTK := y
 CONFIG_EARLY_PL011 := y
 endif
+ifeq ($(CONFIG_EARLY_PRINTK), exynos5)
+EARLY_PRINTK := y
+CONFIG_EARLY_EXYNOS5 := y
+endif
 
 CFLAGS-$(EARLY_PRINTK) += -DEARLY_PRINTK
diff --git a/xen/arch/arm/arm32/Makefile b/xen/arch/arm/arm32/Makefile
index 6af8ca3..90e4eab 100644
--- a/xen/arch/arm/arm32/Makefile
+++ b/xen/arch/arm/arm32/Makefile
@@ -9,3 +9,4 @@ obj-y += domain.o
 
 obj-$(EARLY_PRINTK) += debug.o
 obj-$(CONFIG_EARLY_PL011) += debug-pl011.o
+obj-$(CONFIG_EARLY_EXYNOS5) += debug-exynos5.o
diff --git a/xen/arch/arm/arm32/debug-exynos5.S 
b/xen/arch/arm/arm32/debug-exynos5.S
new file mode 100644
index 0000000..cbe1705
--- /dev/null
+++ b/xen/arch/arm/arm32/debug-exynos5.S
@@ -0,0 +1,81 @@
+/*
+ * xen/arch/arm/arm32/debug-exynos5.S
+ *
+ * Exynos 5 specific debug code
+ *
+ * Copyright (c) 2013 Citrix Systems.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <asm/asm_defns.h>
+
+#define EXYNOS5_UART_BASE_ADDRESS 0x12c20000
+
+.globl early_uart_paddr
+early_uart_paddr: .word EXYNOS5_UART_BASE_ADDRESS
+
+/* Exynos 5 UART initialization
+ * r11: UART base address
+ * Clobber r0-r1 */
+.globl early_uart_init
+early_uart_init:
+        /* init clock */
+        ldr   r1, =0x10020000
+        /* select MPLL (800MHz) source clock */
+        ldr   r0, [r1, #0x250]
+        and   r0, r0, #(~(0xf<<8))
+        orr   r0, r0, #(0x6<<8)
+        str   r0, [r1, #0x250]
+        /* ration 800/(7+1) */
+        ldr   r0, [r1, #0x558]
+        and   r0, r0, #(~(0xf<<8))
+        orr   r0, r0, #(0x7<<8)
+        str   r0, [r1, #0x558]
+
+        mov   r1, #4
+        str   r1, [r11, #0x2c]          /* -> UARTIBRD (Baud divisor fraction) 
*/
+        mov   r1, #53
+        str   r1, [r11, #0x28]          /* -> UARTIBRD (Baud divisor integer) 
*/
+        mov   r1, #3                    /* 8n1 */
+        str   r1, [r11, #0x0]           /* -> (Line control) */
+        ldr   r1, =(1<<2)               /* TX IRQMODE */
+        str   r1, [r11, #0x4]           /* -> (Control Register) */
+        mov   r1, #0x0
+        str   r1, [r11, #0x8]           /* disable FIFO */
+        mov   r1, #0x0
+        str   r1, [r11, #0x0C]          /* no auto flow control */
+        mov   pc, lr
+
+/* Exynos 5 UART wait UART to be ready to transmit
+ * r11: UART base address
+ * Clobber r2 r11 */
+.globl early_uart_ready
+early_uart_ready:
+        ldr   r2, [r11, #0x10]       /* <- UTRSTAT (Flag register) */
+        tst   r2, #(1<<1)            /* Check BUSY bit */
+        beq   early_uart_ready       /* Wait for the UART to be ready */
+        mov   pc, lr
+
+/* Exynos 5 UART transmit character
+ * r2: character to transmit
+ * r11: UART base address */
+.globl early_uart_transmit
+early_uart_transmit:
+        str   r2, [r11, #0x20]       /* -> UTXH (Data Register) */
+        mov   pc, lr
+
+/*
+ * Local variables:
+ * mode: ASM
+ * indent-tabs-mode: nil
+ * End:
+ */
-- 
Julien Grall


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