Re: [Xen-devel] [PATCH] xen: arm: let the compiler choose the dummy register for TLB flush asm

[Tim Deegan <tim@xxxxxxx>]

At 14:21 +0100 on 24 Apr (1366813285), Ian Campbell wrote:
> While staring at some disassembly I noticed that the compiler was jumping
> through hoops to preserve the function argument (in r0) simply so it could use
> r0 as the dummy argument to the tlb flush cp register writes.
> 
> Remove the enforced use of r0 and use an output constraint for the dummy
> register so there is no need to initialise the dummy.

Since we don't care about the register's contents and it's not changed,
can we just drop the variable and constraint entirely?

Tim.

> Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
> ---
>  xen/include/asm-arm/arm32/page.h |    8 ++++----
>  1 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/xen/include/asm-arm/arm32/page.h 
> b/xen/include/asm-arm/arm32/page.h
> index d295316..86940ba 100644
> --- a/xen/include/asm-arm/arm32/page.h
> +++ b/xen/include/asm-arm/arm32/page.h
> @@ -35,7 +35,7 @@ static inline void write_pte(lpae_t *p, lpae_t pte)
>   */
>  static inline void flush_xen_text_tlb(void)
>  {
> -    register unsigned long r0 asm ("r0");
> +    unsigned long dummy;
>      asm volatile (
>          "isb;"                        /* Ensure synchronization with 
> previous changes to text */
>          STORE_CP32(0, TLBIALLH)       /* Flush hypervisor TLB */
> @@ -43,7 +43,7 @@ static inline void flush_xen_text_tlb(void)
>          STORE_CP32(0, BPIALL)         /* Flush branch predictor */
>          "dsb;"                        /* Ensure completion of TLB+BP flush */
>          "isb;"
> -        : : "r" (r0) /*dummy*/ : "memory");
> +        : "=r" (dummy) : : "memory");
>  }
>  
>  /*
> @@ -52,12 +52,12 @@ static inline void flush_xen_text_tlb(void)
>   */
>  static inline void flush_xen_data_tlb(void)
>  {
> -    register unsigned long r0 asm ("r0");
> +    unsigned long dummy;
>      asm volatile("dsb;" /* Ensure preceding are visible */
>                   STORE_CP32(0, TLBIALLH)
>                   "dsb;" /* Ensure completion of the TLB flush */
>                   "isb;"
> -                 : : "r" (r0) /* dummy */: "memory");
> +                 : "=r" (dummy) : : "memory");
>  }
>  
>  /*
> -- 
> 1.7.2.5
> 

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