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Re: [Xen-devel] [PATCH 2/2] iommu/amd: Workaround for ERBT1312

>>> On 18.04.13 at 20:41, <suravee.suthikulpanit@xxxxxxx> wrote:
> The IOMMU interrupt handling in bottom half must clear the PPR log interrupt
> and event log interrupt bits to re-enable the interrupt. This is done by
> writing 1 to the memory mapped register to clear the bit. Due to hardware 
> bug,
> if the driver tries to clear this bit while the IOMMU hardware also setting
> this bit, the conflict will result with the bit being set. If the interrupt
> handling code does not make sure to clear this bit, subsequent changes in 
> the
> event/PPR logs will no longer generating interrupts, and would result if
> buffer overflow. After clearing the bits, the driver must read back
> the register to verify.

The Completion Wait Interrupt bit is unaffected by this erratum?
Or else, is it guaranteed that flush_command_buffer() wouldn't
need a similar fix?


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