[Xen-devel] [PATCH 1/2] iommu/amd: Fix logic for clearing the IOMMU interrupt bits

[<suravee.suthikulpanit@xxxxxxx>]

From: Suravee Suthikulpanit <suravee.suthikulpanit@xxxxxxx>

The IOMMU interrupt bits in the IOMMU status registers are
cleared when writing 1.  Therefore, the existing logic which reads
the register, set the bit, and then writing back the values
could accidentally clear certain bits if it has been set.

The correct logic would just be writing only the value which only
set the interrupt bits, and leave the rest to zeros.

Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@xxxxxxx>
---
 xen/drivers/passthrough/amd/iommu_init.c     |   12 ++++--------
 xen/include/asm-x86/hvm/svm/amd-iommu-defs.h |   13 ++++++++-----
 2 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/xen/drivers/passthrough/amd/iommu_init.c 
b/xen/drivers/passthrough/amd/iommu_init.c
index 73d9ce4..f1af9de 100644
--- a/xen/drivers/passthrough/amd/iommu_init.c
+++ b/xen/drivers/passthrough/amd/iommu_init.c
@@ -623,10 +623,8 @@ static void iommu_check_event_log(struct amd_iommu *iommu)
         iommu_reset_log(iommu, &iommu->event_log, set_iommu_event_log_control);
 
     /* reset interrupt status bit */
-    entry = readl(iommu->mmio_base + IOMMU_STATUS_MMIO_OFFSET);
-    iommu_set_bit(&entry, IOMMU_STATUS_EVENT_LOG_INT_SHIFT);
-
-    writel(entry, iommu->mmio_base + IOMMU_STATUS_MMIO_OFFSET);
+    writel(IOMMU_STATUS_EVENT_LOG_INT_MASK, 
+        iommu->mmio_base + IOMMU_STATUS_MMIO_OFFSET);
 
     spin_unlock_irqrestore(&iommu->lock, flags);
 }
@@ -693,10 +691,8 @@ static void iommu_check_ppr_log(struct amd_iommu *iommu)
         iommu_reset_log(iommu, &iommu->ppr_log, set_iommu_ppr_log_control);
 
     /* reset interrupt status bit */
-    entry = readl(iommu->mmio_base + IOMMU_STATUS_MMIO_OFFSET);
-    iommu_set_bit(&entry, IOMMU_STATUS_PPR_LOG_INT_SHIFT);
-
-    writel(entry, iommu->mmio_base + IOMMU_STATUS_MMIO_OFFSET);
+    writel(IOMMU_STATUS_PPR_LOG_INT_MASK, 
+        iommu->mmio_base + IOMMU_STATUS_MMIO_OFFSET);
 
     spin_unlock_irqrestore(&iommu->lock, flags);
 }
diff --git a/xen/include/asm-x86/hvm/svm/amd-iommu-defs.h 
b/xen/include/asm-x86/hvm/svm/amd-iommu-defs.h
index d2176d0..3e161a5 100644
--- a/xen/include/asm-x86/hvm/svm/amd-iommu-defs.h
+++ b/xen/include/asm-x86/hvm/svm/amd-iommu-defs.h
@@ -385,19 +385,22 @@
 
 /* Status Register*/
 #define IOMMU_STATUS_MMIO_OFFSET               0x2020
-#define IOMMU_STATUS_EVENT_OVERFLOW_MASK       0x00000001
 #define IOMMU_STATUS_EVENT_OVERFLOW_SHIFT      0
-#define IOMMU_STATUS_EVENT_LOG_INT_MASK                0x00000002
+#define IOMMU_STATUS_EVENT_OVERFLOW_MASK       (1 << 
IOMMU_STATUS_EVENT_OVERFLOW_SHIFT)
 #define IOMMU_STATUS_EVENT_LOG_INT_SHIFT       1
-#define IOMMU_STATUS_COMP_WAIT_INT_MASK                0x00000004
+#define IOMMU_STATUS_EVENT_LOG_INT_MASK                (1 << 
IOMMU_STATUS_EVENT_LOG_INT_SHIFT)
 #define IOMMU_STATUS_COMP_WAIT_INT_SHIFT       2
-#define IOMMU_STATUS_EVENT_LOG_RUN_MASK                0x00000008
+#define IOMMU_STATUS_COMP_WAIT_INT_MASK                (1 << 
IOMMU_STATUS_COMP_WAIT_INT_SHIFT)
 #define IOMMU_STATUS_EVENT_LOG_RUN_SHIFT       3
-#define IOMMU_STATUS_CMD_BUFFER_RUN_MASK       0x00000010
+#define IOMMU_STATUS_EVENT_LOG_RUN_MASK                (1 << 
IOMMU_STATUS_EVENT_LOG_RUN_SHIFT)
 #define IOMMU_STATUS_CMD_BUFFER_RUN_SHIFT      4
+#define IOMMU_STATUS_CMD_BUFFER_RUN_MASK       (1 << 
IOMMU_STATUS_CMD_BUFFER_RUN_SHIFT)
 #define IOMMU_STATUS_PPR_LOG_OVERFLOW_SHIFT     5
+#define IOMMU_STATUS_PPR_LOG_OVERFLOW_MASK     (1 << 
IOMMU_STATUS_PPR_LOG_OVERFLOW_SHIFT)
 #define IOMMU_STATUS_PPR_LOG_INT_SHIFT          6
+#define IOMMU_STATUS_PPR_LOG_INT_MASK           (1 << 
IOMMU_STATUS_PPR_LOG_INT_SHIFT)
 #define IOMMU_STATUS_PPR_LOG_RUN_SHIFT          7
+#define IOMMU_STATUS_PPR_LOG_RUN_MASK          (1 << 
IOMMU_STATUS_PPR_LOG_RUN_SHIFT)
 
 /* I/O Page Table */
 #define IOMMU_PAGE_TABLE_ENTRY_SIZE    8
-- 
1.7.10.4



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