Re: [Xen-devel] [PATCH] Re: Question about set up the HCTR at arm32/head.S.

[Ian Campbell <Ian.Campbell@xxxxxxxxxx>]

On Thu, 2013-03-28 at 10:07 +0000, Tim Deegan wrote:
> Hi,
> 
> At 17:42 +0900 on 27 Mar (1364406168), Gihun Jung wrote:
> > It described "PT walks are write-back, no-write-allocate in both cache
> > level": load 0x80002500 to r0.
> > At 4rd position of 0x800025000 (i.e. 5 = b0101), that is my question
> > point. According to armv7 architecture manual, that bits should be b11
> > respectively for both cache levels to enable "write-back,
> > no-write-allocate", but, in the code, it seems set up to "write-back,
> > write-allocate" for both cache levels. I am not sure which one is
> > correct: comment or code?
> 
> Well spotted - the code is correct.
> 
> Thanks,
> 
> Tim.
> 
> --------
> 
> arm: fix comment in HTCR setup.
> 
> Reported-by: Gihun Jung <gihun.jung@xxxxxxxxx>
> Signed-off-by: Tim Deegan <tim@xxxxxxx>

Acked+applied, thanks!



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