Re: [Xen-devel] [PATCH 17/45] xen: arm64: xchg and cmpxchg

[Tim Deegan <tim@xxxxxxx>]

At 17:06 +0000 on 07 Feb (1360256782), Ian Campbell wrote:
> On Thu, 2013-02-07 at 16:48 +0000, Tim Deegan wrote:
> > At 15:56 +0000 on 23 Jan (1358956583), Ian Campbell wrote:
> > > Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
> > > ---
> > >  xen/include/asm-arm/arm32/system.h |  115 ++++++++++++++++++++++++++
> > >  xen/include/asm-arm/arm64/system.h |  155 
> > > ++++++++++++++++++++++++++++++++++++
> > >  xen/include/asm-arm/system.h       |  114 --------------------------
> > >  3 files changed, 270 insertions(+), 114 deletions(-)
> > > 
> > > --- a/xen/include/asm-arm/arm64/system.h
> > > +++ b/xen/include/asm-arm/arm64/system.h
> > > @@ -17,6 +17,161 @@
> > >  #define smp_rmb()       asm volatile("dmb ishld" : : : "memory")
> > >  #define smp_wmb()       asm volatile("dmb ishst" : : : "memory")
> > >  
> > > +
> > > +extern void __bad_xchg(volatile void *, int);
> > > +
> > > +static inline unsigned long __xchg(unsigned long x, volatile void *ptr, 
> > > int size)
> > > +{
> > > +        unsigned long ret, tmp;
> > > +
> > > +        switch (size) {
> > > +        case 1:
> > > +                asm volatile("//        __xchg1\n"
> > > +                "1:     ldaxrb  %w0, [%3]\n"
> > > +                "       stlxrb  %w1, %w2, [%3]\n"
> > 
> > Why are these using acquire/release ops (i.e. why not LDXR/STXR)?
> 
> I nicked this from Linux ;-)
> 
> > The 32-bit equivalent doesn't have any memory barriers. 
> 
> You mean does? There is a smp_mb() before and after in that
> implementation.

Argh, so there is.  I jujst didn't see it for some reason.  So,

Acked-by: Tim Deegan <tim@xxxxxxx>

Tim.

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