Re: [Xen-devel] [PATCH 14/45] xen: arm64: TLB flushes.

[Ian Campbell <Ian.Campbell@xxxxxxxxxx>]

On Thu, 2013-02-07 at 16:34 +0000, Tim Deegan wrote:
> At 15:56 +0000 on 23 Jan (1358956580), Ian Campbell wrote:
> > --- a/xen/include/asm-arm/arm64/page.h
> > +++ b/xen/include/asm-arm/arm64/page.h
> > @@ -20,6 +20,58 @@ static inline void write_pte(lpae_t *p, lpae_t pte)
> >  
> >  #define __flush_xen_dcache_one(va) asm volatile ("dc cvac, %0;" : : "r" 
> > (va))
> >  
> > +/*
> > + * Flush all hypervisor mappings from the TLB
> > + * This is needed after changing Xen code mappings.
> > + *
> > + * The caller needs to issue the necessary DSB and D-cache flushes
> > + * before calling flush_xen_text_tlb.
> > + */
> > +static inline void flush_xen_text_tlb(void)
> > +{
> > +    asm volatile (
> > +        "isb;"       /* Ensure synchronization with previous changes to 
> > text */
> > +        "tlbi   alle2;"                 /* Flush hypervisor TLB */
> > +        "ic     iallu;"                 /* Flush I-cache */
> > +        "dsb    sy;"                    /* Ensure completion of TLB+BP 
> > flush */
> 
> No BP flush operation on arm64?

Correct.

> If so, I think this comment needs updating. 

Yup, I think I got most of them but missed this one.

> 
> > +        "isb;"
> > +        : : : "memory");
> > +}
> > +
> > +/*
> > + * Flush all hypervisor mappings from the data TLB. This is not
> > + * sufficient when changing code mappings or for self modifying code.
> > + */
> > +static inline void flush_xen_data_tlb(void)
> > +{
> > +    asm volatile (
> > +        "dsb    sy;"                    /* Ensure visibility of PTE writes 
> > */
> > +        "tlbi   alle2;"                 /* Flush hypervisor TLB */
> > +        "dsb    sy;"                    /* Ensure completion of TLB flush 
> > */
> > +        "isb;"
> > +        : : : "memory");
> > +}
> > +
> > +/*
> > + * Flush one VA's hypervisor mappings from the data TLB. This is not
> > + * sufficient when changing code mappings or for self modifying code.
> > + */
> > +static inline void flush_xen_data_tlb_va(vaddr_t va)
> > +{
> > +    asm volatile(
> > +        "dsb    sy;"                    /* Ensure preceding are visible */
> > +        "tlbi   vae2, %0;"
> > +        "dsb    sy;"                    /* Ensure completion of the TLB 
> > flush */
> > +        "isb;"
> > +        : : "r" (va>>PAGE_SHIFT) : "memory");
> > +}
> > +
> > +/* Flush all non-hypervisor mappings from the TLB */
> > +static inline void flush_guest_tlb(void)
> > +{
> > +    asm volatile("tlbi alle1,ns" : : : "memory");
> > +}
> 
> What does the ',ns' do here?

Er, I can't remember and I can't find it anywhere in the docs. It might
be a typo of "is" which somehow makes it past gas. Or maybe something to
do with non-secure e1?

> And is the memory clobber required?  (And if so, don't we need a DSB or two 
> as well?)

The 32-bit stuff doesn't have one either.

But then it appears that this function is never called anyway...

Ian.



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