|
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH 14/45] xen: arm64: TLB flushes.
Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
---
xen/include/asm-arm/arm32/page.h | 54 ++++++++++++++++++++++++++++++++++++++
xen/include/asm-arm/arm64/page.h | 52 ++++++++++++++++++++++++++++++++++++
xen/include/asm-arm/page.h | 54 --------------------------------------
3 files changed, 106 insertions(+), 54 deletions(-)
diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h
index dfbf4b0..d4852f9 100644
--- a/xen/include/asm-arm/arm32/page.h
+++ b/xen/include/asm-arm/arm32/page.h
@@ -25,6 +25,60 @@ static inline void write_pte(lpae_t *p, lpae_t pte)
#define __flush_xen_dcache_one(va) WRITE_CP32((uint32_t) va, DCCMVAC)
+/*
+ * Flush all hypervisor mappings from the TLB and branch predictor.
+ * This is needed after changing Xen code mappings.
+ *
+ * The caller needs to issue the necessary DSB and D-cache flushes
+ * before calling flush_xen_text_tlb.
+ */
+static inline void flush_xen_text_tlb(void)
+{
+ register unsigned long r0 asm ("r0");
+ asm volatile (
+ "isb;" /* Ensure synchronization with previous
changes to text */
+ STORE_CP32(0, TLBIALLH) /* Flush hypervisor TLB */
+ STORE_CP32(0, ICIALLU) /* Flush I-cache */
+ STORE_CP32(0, BPIALL) /* Flush branch predictor */
+ "dsb;" /* Ensure completion of TLB+BP flush */
+ "isb;"
+ : : "r" (r0) /*dummy*/ : "memory");
+}
+
+/*
+ * Flush all hypervisor mappings from the data TLB. This is not
+ * sufficient when changing code mappings or for self modifying code.
+ */
+static inline void flush_xen_data_tlb(void)
+{
+ register unsigned long r0 asm ("r0");
+ asm volatile("dsb;" /* Ensure preceding are visible */
+ STORE_CP32(0, TLBIALLH)
+ "dsb;" /* Ensure completion of the TLB flush */
+ "isb;"
+ : : "r" (r0) /* dummy */: "memory");
+}
+
+/*
+ * Flush one VA's hypervisor mappings from the data TLB. This is not
+ * sufficient when changing code mappings or for self modifying code.
+ */
+static inline void flush_xen_data_tlb_va(unsigned long va)
+{
+ asm volatile("dsb;" /* Ensure preceding are visible */
+ STORE_CP32(0, TLBIMVAH)
+ "dsb;" /* Ensure completion of the TLB flush */
+ "isb;"
+ : : "r" (va) : "memory");
+}
+
+/* Flush all non-hypervisor mappings from the TLB */
+static inline void flush_guest_tlb(void)
+{
+ register unsigned long r0 asm ("r0");
+ WRITE_CP32(r0 /* dummy */, TLBIALLNSNH);
+}
+
#endif /* __ASSEMBLY__ */
#endif /* __ARM_ARM32_PAGE_H__ */
diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h
index 7b297b5..e69b4a4 100644
--- a/xen/include/asm-arm/arm64/page.h
+++ b/xen/include/asm-arm/arm64/page.h
@@ -20,6 +20,58 @@ static inline void write_pte(lpae_t *p, lpae_t pte)
#define __flush_xen_dcache_one(va) asm volatile ("dc cvac, %0;" : : "r" (va))
+/*
+ * Flush all hypervisor mappings from the TLB
+ * This is needed after changing Xen code mappings.
+ *
+ * The caller needs to issue the necessary DSB and D-cache flushes
+ * before calling flush_xen_text_tlb.
+ */
+static inline void flush_xen_text_tlb(void)
+{
+ asm volatile (
+ "isb;" /* Ensure synchronization with previous changes to text */
+ "tlbi alle2;" /* Flush hypervisor TLB */
+ "ic iallu;" /* Flush I-cache */
+ "dsb sy;" /* Ensure completion of TLB+BP flush */
+ "isb;"
+ : : : "memory");
+}
+
+/*
+ * Flush all hypervisor mappings from the data TLB. This is not
+ * sufficient when changing code mappings or for self modifying code.
+ */
+static inline void flush_xen_data_tlb(void)
+{
+ asm volatile (
+ "dsb sy;" /* Ensure visibility of PTE writes */
+ "tlbi alle2;" /* Flush hypervisor TLB */
+ "dsb sy;" /* Ensure completion of TLB flush */
+ "isb;"
+ : : : "memory");
+}
+
+/*
+ * Flush one VA's hypervisor mappings from the data TLB. This is not
+ * sufficient when changing code mappings or for self modifying code.
+ */
+static inline void flush_xen_data_tlb_va(vaddr_t va)
+{
+ asm volatile(
+ "dsb sy;" /* Ensure preceding are visible */
+ "tlbi vae2, %0;"
+ "dsb sy;" /* Ensure completion of the TLB flush
*/
+ "isb;"
+ : : "r" (va>>PAGE_SHIFT) : "memory");
+}
+
+/* Flush all non-hypervisor mappings from the TLB */
+static inline void flush_guest_tlb(void)
+{
+ asm volatile("tlbi alle1,ns" : : : "memory");
+}
+
#endif /* __ASSEMBLY__ */
#endif /* __ARM_ARM64_PAGE_H__ */
diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h
index 3b6b0f9..05b7caa 100644
--- a/xen/include/asm-arm/page.h
+++ b/xen/include/asm-arm/page.h
@@ -269,60 +269,6 @@ static inline void flush_xen_dcache_va_range(void *p,
unsigned long size)
} \
} while (0)
-/*
- * Flush all hypervisor mappings from the TLB and branch predictor.
- * This is needed after changing Xen code mappings.
- *
- * The caller needs to issue the necessary DSB and D-cache flushes
- * before calling flush_xen_text_tlb.
- */
-static inline void flush_xen_text_tlb(void)
-{
- register unsigned long r0 asm ("r0");
- asm volatile (
- "isb;" /* Ensure synchronization with previous
changes to text */
- STORE_CP32(0, TLBIALLH) /* Flush hypervisor TLB */
- STORE_CP32(0, ICIALLU) /* Flush I-cache */
- STORE_CP32(0, BPIALL) /* Flush branch predictor */
- "dsb;" /* Ensure completion of TLB+BP flush */
- "isb;"
- : : "r" (r0) /*dummy*/ : "memory");
-}
-
-/*
- * Flush all hypervisor mappings from the data TLB. This is not
- * sufficient when changing code mappings or for self modifying code.
- */
-static inline void flush_xen_data_tlb(void)
-{
- register unsigned long r0 asm ("r0");
- asm volatile("dsb;" /* Ensure preceding are visible */
- STORE_CP32(0, TLBIALLH)
- "dsb;" /* Ensure completion of the TLB flush */
- "isb;"
- : : "r" (r0) /* dummy */: "memory");
-}
-
-/*
- * Flush one VA's hypervisor mappings from the data TLB. This is not
- * sufficient when changing code mappings or for self modifying code.
- */
-static inline void flush_xen_data_tlb_va(unsigned long va)
-{
- asm volatile("dsb;" /* Ensure preceding are visible */
- STORE_CP32(0, TLBIMVAH)
- "dsb;" /* Ensure completion of the TLB flush */
- "isb;"
- : : "r" (va) : "memory");
-}
-
-/* Flush all non-hypervisor mappings from the TLB */
-static inline void flush_guest_tlb(void)
-{
- register unsigned long r0 asm ("r0");
- WRITE_CP32(r0 /* dummy */, TLBIALLNSNH);
-}
-
/* Print a walk of an arbitrary page table */
void dump_pt_walk(lpae_t *table, paddr_t addr);
--
1.7.2.5
_______________________________________________
Xen-devel mailing list
Xen-devel@xxxxxxxxxxxxx
http://lists.xen.org/xen-devel
|
 |
Lists.xenproject.org is hosted with RackSpace, monitoring our |