Re: [Xen-devel] [PATCH 2 of 5] rombios/ata: Do not wait for BSY to be set

[Mats Petersson <mats.petersson@xxxxxxxxxx>]

On 27/11/12 16:46, Tim Deegan wrote:
> At 16:41 +0000 on 26 Nov (1353948093), Andrew Cooper wrote:
> > I can't find any guarantee in the ATA specification that this will happen, and 
> > it
> > certainly does not with Qemu.  SeaBIOS has replaced it with a call to udelay(5)
> > instead.
> >
> > As rombios does not have an equivalent udelay(), replace the wait with a write
> > to port 0x80 which is whitelisted by Xen for 'a small delay'.
> Does this actually do anything useful?  I'd guess that on qemu the extra
> outb has no effect and on real hardware that needed a delay here, one
> I/O cycle would not be enough.
I believe it's quite a significant delay also on real hardware - but 
real hardware isn't booting 100s of OSes in short succession [typically, 
at least], as it has to trickle through all the buses and stuff down to 
the southbridge. Which is quite a large number of cycles even in a 
modern system.
It is typically used to ensure that "some other bus cycle" goes in 
between two IO operations that affect each other, where the hardware is 
run by a significantly slower processor than the CPU - a 16MHz 16-bit 
processor or some such. It allows the hardware to "react" to the IO 
instructions, and change state. Yes, it's daft, and we can't fix that.
In QEMU, it's not going to matter, as the "hardware" is idealised and 
don't have the same timing restrictions of REAL hardware.
--
mats
> Tim.
>
> > This causes roughly 42k fewer traps to Qemu, which is very roughly 10% of the
> > number of traps during boot of a Win7 guest.
> >
> > Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
> >
> > diff -r 1728fb789940 -r c223c044afbf tools/firmware/rombios/rombios.c
> > --- a/tools/firmware/rombios/rombios.c
> > +++ b/tools/firmware/rombios/rombios.c
> > @@ -2914,8 +2914,8 @@ Bit16u device;
> >   // 8.2.1 (a) -- set SRST in DC
> >     outb(iobase2+ATA_CB_DC, ATA_CB_DC_HD15 | ATA_CB_DC_NIEN | ATA_CB_DC_SRST);
> >   
> > -// 8.2.1 (b) -- wait for BSY
> > -  await_ide(BSY, iobase1, 20);
> > +// 8.2.1 (b) -- wait
> > +  outb(0x80, 0x00);
> >   
> >   // 8.2.1 (f) -- clear SRST
> >     outb(iobase2+ATA_CB_DC, ATA_CB_DC_HD15 | ATA_CB_DC_NIEN);
> >
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