Re: [Xen-devel] [PATCH] Xen/MCE: adjust for future new vMCE model

[Christoph Egger <Christoph.Egger@xxxxxxx>]

On 07/05/12 20:38, Liu, Jinsong wrote:

> Luck, Tony wrote:
>>> I'm not sure if AMD has these 2 bits in MCG_CAP. Could you tell me
>>> where can I get 
>>> AMD's *latest* open doc (something like amd architecture programmer
>>> manual)? 
>>>
>>> If AMD has these 2 bits, it's safe to set them independent of host
>>> capability -- guest 
>>> will just think it running on a platform w/ some events *possilbe*
>>> (though actually 
>>> may never occur), hypervisor know what actually occur and has the
>>> flexibility to 
>>> decide what it would like to inject to guest.
>>>
>>> This code is only used by Intel, and it's only for not blocking
>>> future vMCE, so it just do minimal necessary update. 
>>
>> I think you should be very wary of creating "Franken-machines" that
>> look half AMD (according to CPUID) and half Intel (according to
>> MCG_CAP). You can look at the Linux code and check whether we always
>> make sensible decisions when presented with 
>> such a system ... but you may not have that luxury with other guest
>> operating systems. My general mantra is that untested code paths have
>> bugs. 
>>
>> -Tony
> 
> Yes, I indeed concern AMD cpuid vs. Intel MCG_CAP. Do you suggest

> that we'd better separately provide Intel's and AMD's vMCE interface?

That is no reason to have seperate vmce_intel.c and vmce_amd.c files.

>From the last patch in function vmce_init_msr():

+    g_mcg_cap = MCG_TES_P | MCG_SER_P | GUEST_BANK_NUM;
+

I think, this should be changed to:

     g_mcg_cap = GUEST_BANK_NUM;
     if (cpu_vendor == X86_VENDOR_INTEL)
         g_mcg_cap |=  MCG_TES_P | MCG_SER_P;

Another question:

What happens when a guest access the MSRs
0xc0000408, 0xc0000409 and 0xc000040a ?

Christoph


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