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Re: [Xen-devel] Help needed debugging "EPT Misconfiguration" exception on Intel CPU



At 17:08 +0000 on 26 Jan (1327597687), Kalev, Leonid wrote:
> (XEN) EPT Misconfiguration, gpa=00000000feffe000
> (XEN) domain->...->eptp   = 0x431b3d01e
> (XEN) vmread(EPT_POINTER) = 0x431b3d01e
> 
>     EPTP bits:
>     0-2   = 6; mem type (0 = UC, 6=WB, all other = invalid)
>     5-3   = 3 (should be = 3 (walk length - 1))
>     6-11  = 0 reserved
>     12-39 = 0x431b3d; addr of EPT PML4
>     40-64 = 0 ; reserved (40 is the addr sz of the CPU here, may vary on 
> other CPUs, 
> max=48)
> 
> (XEN) p2m-ept.c:649:d3 Walking EPT tables for domain 3 gfn feffe
> (XEN) p2m-ept.c:668:d3  epte 1c00000431b3c007
>                                                 0-2 = 7: access allowed: rwx
>                                                 3-7 = 0: reserved
>                            8-11 = 0: ignored
>                                                 x-12 = 431b3c: address of 
> next level EPT
>                            51-x - 0
>                            52-63 - ignored
> (XEN) p2m-ept.c:668:d3  epte 1c000004374fb007
> (XEN) p2m-ept.c:668:d3  epte 1c000004374fa007
> (XEN) p2m-ept.c:668:d3  epte 1c10000c213ee037 0-2 = 7: rwx
>                                     10000000000 (nb: addr size limit - 40 
> bits for
>                                                  this CPU, we're way below)
>                                                 3-5 = 6: type (0 = UC; 1 = 
> WC; 4 = WT;
>                                                          5 = WP; 6 = WB)
>                            6   = 0:
>                            7-11 =0: (ignored)
>                            mfn=c213ee, (looks valid, mem extends from 100000 
> to 
> c40000, see mem map below)
>                            52=1;  52-63 should be ignored

Yeah, those entries look fine.  Certainly they don't have any of the
problems listed in section 25.2.3.1 of the SDM under "EPT
Misconfigurations", so I suspect there must be something odd about the
non-production CPU you're using.  

Tim.

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