[Xen-devel] [PATCH 0/6] X86 new features expose and PCID/INVPCID

["Liu, Jinsong" <jinsong.liu@xxxxxxxxx>]

These patches expose 6 X86 new features to dom0/pv/hvm guest, and implement 
PCID/INVPCID for hap hvm.

Intel recently add 6 X86 new features, refer to 
http://software.intel.com/file/36945
Patch 1/2 are to expose these new features to dom0, pv, and hvm.

Intel also add a new instruction INVPCID to invalidate TLB. Refer latest Intel 
SDM 
http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html
Patch 3/4 are to disable PCID/INVPCID for dom0 and pv. Exposing them into dom0 
and pv may result in performance regression, and it would trigger GP or UD 
depending on whether platform suppport INVPCID or not.
Patch 5/6 are to handle PCID/INVPCID for hvm: For hap hvm, we enable 
PCID/INVPCID, since no need to intercept INVPCID, and we just set INVPCID 
non-root behavior as running natively; For shadow hvm, we disable PCID/INVPCID, 
otherwise we need to emulate INVPCID at vmm by setting INVPCID non-root 
behavior as vmexit.

Thanks,
Jinsong

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