RE: [Xen-devel] [PATCH] Enable TSC_RELIABLE for AMD servers

["Langsdorf, Mark" <mark.langsdorf@xxxxxxx>]

The TSC on AMD processors with the invariant TSC
bit is reliable per Xen's definition of the term.

Acked-by: Mark Langsdorf <mark.langsdorf@xxxxxxx> 

-Mark Langsdorf
Operating System Research Center
AMD

> -----Original Message-----
> From: xen-devel-bounces@xxxxxxxxxxxxxxxxxxx 
> [mailto:xen-devel-bounces@xxxxxxxxxxxxxxxxxxx] On Behalf Of 
> Dan Magenheimer
> Sent: Tuesday, October 20, 2009 10:05 AM
> To: Xen-Devel (E-mail)
> Cc: Langsdorf, Mark; Keir Fraser
> Subject: [Xen-devel] [PATCH] Enable TSC_RELIABLE for AMD servers
> 
> (Mark, please ack)
> 
> Enable TSC_RELIABLE for AMD servers
> 
> Except for a published BIOS errata on family 11h processors,
> all AMD servers that have the Invariant TSC bit set have
> a reliable TSC so Xen should not write to the TSC.
> 
> Signed-off-by: Dan Magenheimer <dan.magenheimer@xxxxxxxxxx>
> 
> 
> diff -r d7d7f978d704 xen/arch/x86/cpu/amd.c
> --- a/xen/arch/x86/cpu/amd.c  Tue Oct 20 14:36:01 2009 +0100
> +++ b/xen/arch/x86/cpu/amd.c  Tue Oct 20 08:55:53 2009 -0600
> @@ -465,6 +465,8 @@ static void __devinit init_amd(struct cp
>               if (c->x86_power & (1<<8)) {
>                       set_bit(X86_FEATURE_CONSTANT_TSC, 
> c->x86_capability);
>                       set_bit(X86_FEATURE_NONSTOP_TSC, 
> c->x86_capability);
> +                     if (c->x86 != 0x11)
> +                             
> set_bit(X86_FEATURE_TSC_RELIABLE, c->x86_capability);
>               }
>       }
> 
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> 

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