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[Xen-devel] RE: [PATCH] trust new architecturally-defined TSC Invariant bit on Intel systems

> > Trust new architecturally-defined TSC Invariant bit (on
> > Intel systems only for now, AMD TBD).
> > 
> > Signed-off-by: Dan Magenheimer <dan.magenheimer@xxxxxxxxxx>
> Reworked this a bunch, so we always look to the X86_FEATURE_ 
> bits to decide
> what to do, rather than also needing to interpret a growing 
> bunch of boot
> flags.

Eyeballed in staging, looks good, but...

If TSC is reliable, is it still necessary to rendezvous?
I thought the rendezvous was only needed if the slopes
differ (but not sure I've thought it all the way through).
No sense stealing all those pcpu cycles to rendezvous if
it's not necessary, especially on a large system.
(Maybe TSC reliability IS useful for Xen, not just for
exposing to userland :-)

Also, if TSC is constant and no deep-C events have
happened (need a global counter), the rendezvous
might also be avoidable.


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