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RE: Re[2]: [Xen-devel] No VT-d with Xen 3.3/3.4rc3 on Intel-Board DQ45CB


  • To: Tim Kaufmann <tk@xxxxxxxxxx>, xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxx>
  • From: "Cui, Dexuan" <dexuan.cui@xxxxxxxxx>
  • Date: Fri, 22 May 2009 10:45:48 +0800
  • Accept-language: zh-CN, en-US
  • Acceptlanguage: zh-CN, en-US
  • Cc: Anthony Bosio <anthony@xxxxxxxxxx>, "Matthias P. Würfl" <mpw@xxxxxxxxxx>, Eikelenboom <linux@xxxxxxxxxxxxxx>, Sander
  • Delivery-date: Thu, 21 May 2009 19:47:16 -0700
  • List-id: Xen developer discussion <xen-devel.lists.xensource.com>
  • Thread-index: AcnZkq6BH8CIBGZ8QW6xrcEqdh5ekwA86aIA
  • Thread-topic: Re[2]: [Xen-devel] No VT-d with Xen 3.3/3.4rc3 on Intel-Board DQ45CB

Tim Kaufmann wrote:
> Am 20.05.2009 um 21:38 schrieb Sander Eikelenboom:
> 
>> Are you problems with VT-D and the Intel-Board DQ45CB fixed ?
> 
> Almost.
> 
> In fact, the hang occurs with RAM > 2 GB and is caused by a BIOS
> error. As one of the Intel guys on this list told me after several
> tests:
Actually the VT-d support of the motherboard is good.
The issue is caused by a small mistake in RMRR reporting in BIOS.

> 
>> Please let me offer more technical details about the hang you suffer
>> from: Due to the very very big and bad rmrr->end_address
>> 0xffffffffbfffffff, in setup_dom0_rmrr() ->
>> iommu_prepare_rmrr_dev(),  intel_iommu_map_page() is invoked too too
>> many times and you see the hang...
> 
> I already received a patch for Xen 3.4RC4 which I can properly enable
> VT-d with. But there'll be a BIOS-Update soon, they promised.

Yes, I think a BIOS update should come out soon.
For now, we can use the following small patch as a workaround. :-)

diff -r f80cf52a4fb6 xen/drivers/passthrough/vtd/iommu.c
--- a/xen/drivers/passthrough/vtd/iommu.c       Thu Apr 30 14:34:15 2009 +0100
+++ b/xen/drivers/passthrough/vtd/iommu.c       Mon May 18 16:12:14 2009 +0800
@@ -1541,6 +1541,8 @@ static int iommu_prepare_rmrr_dev(struct
     ASSERT(spin_is_locked(&pcidevs_lock));
     ASSERT(rmrr->base_address < rmrr->end_address);
     
+    if ( (rmrr->end_address >> 32) & 0x80000000 )
+        rmrr->end_address &= 0xFFFFFFFF;
     base = rmrr->base_address & PAGE_MASK_4K;
     base_pfn = base >> PAGE_SHIFT_4K;
     end = PAGE_ALIGN_4K(rmrr->end_address);


Thanks,
-- Dexuan


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