RE: [Xen-devel] Time skew on HP DL785 (and possibly other boxes)

["Tian, Kevin" <kevin.tian@xxxxxxxxx>]

>From: Keir Fraser [mailto:keir.fraser@xxxxxxxxxxxxx] 
>Sent: 2009年4月5日 15:56
>
>One concern I have however, is Intel's 
>X86_FEATURE_CONSTANT_TSC logic. This
>was added by them to prevent TSCs from diverging due to Cx deep sleep
>states, by observing that usually all TSCs will tick at the 
>same exact rate,

Here one correction is, that constant tsc logic is introduced for 
P-states instead of C-states, to have TSC always stepping in 
constant pace on a given processor, regardless of whatever 
opertion point is being requested by cpufreq governor. It 
doesn't say anything that all TSCs tick at same rate however.

>so all that needs to be done is to rewrite all AP TSCs to that 
>of the BP
>periodically. This seems to work well on small systems, but 
>the trigger for
>this mode is rather suspicious. CONSTANT_TSC feature means 
>that a CPU's TSC
>is invariant across frequency/voltage changes -- it *doesn't* 
>mean that all
>TSCs across a large MP box are at matched frequency! I wonder 

You're exactly right here. To use it does require that all cpus
are driven by a single crystal, which is not true for a large
system with multipe crystals. So this approach (sync all TSCs
to minimize skews caused by TSC stop from deep C-states)
doesn't work in all cases.

>whether this
>optimisation will bite us on big iron? Probably it ought to 
>disable itself
>if it detects significant TSC divergence, or at the very least maybe we
>should add a command-line option to disable (or enable?) it.

I guess thing won't be that worse in this C-state specific
area. Large system based on Intel core-i7 processors or later
always have invariant tsc feature (non-stop tsc) integrated, and
thus no software recovery is required, while in the meantime,
iirc, previous large scale servers don't have deep C-state (>=C3)
implemented and so it's not an issue too. :-)

Thanks,
Kevin

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