# HG changeset patch
# User Alex Williamson <alex.williamson@xxxxxx>
# Date 1192222177 21600
# Node ID 52d9f5028397081990791e633aa12e112bfe2677
# Parent  4e45ba84a1faf22ef59a4dc3389a3e0424a48724
[IA64] Fix TLB insertion for subpaging

Without this patch, Longhorn is sure to hang up.  .NET application
might hit this bug.  itc.i instruction is repeated forever, because
TLB entry with smaller page size is volatile.

Signed-off-by: Kouya Shimura <kouya@xxxxxxxxxxxxxx>
xen-unstable changeset: 16177:52d9f5028397081990791e633aa12e112bfe2677
xen-unstable date: Fri Oct 12 14:49:37 2007 -0600

diff -r 4e45ba84a1fa -r 52d9f5028397 xen/arch/ia64/vmx/vtlb.c
--- a/xen/arch/ia64/vmx/vtlb.c	Fri Oct 12 14:36:37 2007 -0600
+++ b/xen/arch/ia64/vmx/vtlb.c	Fri Oct 12 14:49:37 2007 -0600
@@ -572,13 +572,16 @@ int thash_purge_and_insert(VCPU *v, u64 
         }
         else {
             u64 psr;
-            phy_pte  &= ~PAGE_FLAGS_RV_MASK;
-            psr = ia64_clear_ic();
-            ia64_itc(type + 1, ifa, phy_pte, ps);
-            ia64_set_psr(psr);
-            ia64_srlz_i();
-            // ps < mrr.ps, this is not supported
-            // panic_domain(NULL, "%s: ps (%lx) < mrr.ps \n", __func__, ps);
+
+            vtlb_insert(v, pte, itir, ifa);
+            vcpu_quick_region_set(PSCBX(v, tc_regions), ifa);
+            if (!(pte & VTLB_PTE_IO)) {
+                phy_pte  &= ~PAGE_FLAGS_RV_MASK;
+                psr = ia64_clear_ic();
+                ia64_itc(type + 1, ifa, phy_pte, ps);
+                ia64_set_psr(psr);
+                ia64_srlz_i();
+            }
         }
     }
     else{