diff -r 089696e0c603 xen/arch/x86/hvm/svm/svm.c
--- a/xen/arch/x86/hvm/svm/svm.c	Thu May 17 11:42:46 2007 +0100
+++ b/xen/arch/x86/hvm/svm/svm.c	Mon May 21 19:09:59 2007 +0200
@@ -177,6 +177,14 @@ static inline int long_mode_do_msr_write
         if ( !svm_paging_enabled(v) )
             vmcb->efer &= ~(EFER_LME | EFER_LMA);
 
+        break;
+
+    case MSR_K8_MC4_MISC: /* Threshold register */
+        /* MCA/MCE: Threshold register is reported to be locked.
+         *   So we ignore all write accesses. This behaviour
+         *   matches real HW, so guests should have no problem
+         *   with this.
+         */
         break;
 
     default:
@@ -2062,6 +2070,14 @@ static inline void svm_do_msr_access(
             msr_content = v->arch.hvm_svm.cpu_shadow_efer;
             break;
 
+        case MSR_K8_MC4_MISC: /* Threshold register */
+            /* MCA/MCE: We report HVM guests, threshold register
+             *   is not available for OS use. The value means,
+             *   the msr has been locked by the BIOS.
+             */
+            msr_content = 0x2000000000000000ULL;
+            break;
+
         default:
             if ( rdmsr_hypervisor_regs(ecx, &eax, &edx) ||
                  rdmsr_safe(ecx, eax, edx) == 0 )
diff -r 089696e0c603 xen/include/asm-x86/msr.h
--- a/xen/include/asm-x86/msr.h	Thu May 17 11:42:46 2007 +0100
+++ b/xen/include/asm-x86/msr.h	Mon May 21 19:08:35 2007 +0200
@@ -216,6 +216,28 @@ static inline void write_efer(__u64 val)
 #define MSR_IA32_MC0_STATUS		0x401
 #define MSR_IA32_MC0_ADDR		0x402
 #define MSR_IA32_MC0_MISC		0x403
+
+/* K8 MC MSR */
+#define MSR_K8_MC1_CTL			0x404
+#define MSR_K8_MC1_STATUS		0x405
+#define MSR_K8_MC1_ADDR			0x406
+#define MSR_K8_MC1_MISC			0x407
+
+#define MSR_K8_MC2_CTL			0x408
+#define MSR_K8_MC2_STATUS		0x409
+#define MSR_K8_MC2_ADDR			0x40A
+#define MSR_K8_MC2_MISC			0x40B
+
+#define MSR_K8_MC3_CTL			0x40C
+#define MSR_K8_MC3_STATUS		0x40D
+#define MSR_K8_MC3_ADDR			0x40E
+#define MSR_K8_MC3_MISC			0x40F
+
+#define MSR_K8_MC4_CTL			0x410
+#define MSR_K8_MC4_STATUS		0x411
+#define MSR_K8_MC4_ADDR			0x412
+#define MSR_K8_MC4_MISC			0x413
+
 
 /* Pentium IV performance counter MSRs */
 #define MSR_P4_BPU_PERFCTR0 		0x300