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xen-ppc-devel
Re: [XenPPC] [PATCH] Disable DPM until code is audited
On Dec 2, 2006, at 2:37 AM, Segher Boessenkool wrote:
Do not set the NAP and DPM bits in HID0 until we have had a
chance to
audit the safe halt and idle loop code. Not setting these bits
allows
the model 884241X JS20 blade in TRL to boot correctly, and
possibly also
the Maple in YKT. Thanks to Jimi for his help in this matter.
Is the DPM change required? I never saw any problems
here... NAP and other power saving modes can cause
problems for sure (for example, on pre-970MP 970s, some
power saving modes require flushing the L2 before entering
that mode, etc.)
Most JS20 and JS21 have DPM disabled on the board,
What does this mean? SLOF/js2x enables DPM always, for
example; there is no hardware override that I'm aware of.
According to S9.9 of 970FX UM:
Dynamic power management can be disabled in the RAS units by
asserting bit[0]
in the JTAG register with modifier address 0x000800.
which is why we have not seen any SMP problems with them. However
the Maple-D and the JS20 model Amos cites both have had problems
with the one of these two modes. That model seems to be the
newest JS20 we've run on.
Sounds like the problem manifests itself on all 970FX and
no other CPUs from the 970 family.
I was under the impression that we had other 970FX js20s but perhaps
we do not
We'll have to brush up on errata before we enable this one again.
Yeah; errata and other chip differences.
My question remains: did you try with NAP disabled and
DPM enabled?
I see, so:
HID0[NAP]=1
HID0[DPM]=1
MSR[POW]=1
is NAP and is different than:
HID0[NAP]=0
HID0[DPM]=1
MSR[POW]=1
which is something else?
Sure I'll try that.
-JX
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