# HG changeset patch # User Tristan Gingold # Date 1181622998 -7200 # Node ID 9ca15906b0571dce96478caac93e75964bb28d05 # Parent 7e8534c5598abc73d40475132256d9890771d4d9 Change virtual address of XEN UC indentity area. Signed-off-by: Tristan Gingold diff -r 7e8534c5598a -r 9ca15906b057 xen/arch/ia64/vmx/vmx_ivt.S --- a/xen/arch/ia64/vmx/vmx_ivt.S Tue Jun 12 06:07:46 2007 +0200 +++ b/xen/arch/ia64/vmx/vmx_ivt.S Tue Jun 12 06:36:38 2007 +0200 @@ -320,14 +320,12 @@ vmx_alt_itlb_miss_1: movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff) ;; and r19=r19,r16 // clear ed, reserved bits, and PTE control bits - shr.u r18=r16,55 // move address bit 59 to bit 4 - ;; - and r18=0x10,r18 // bit 4=address-bit(61) + extr.u r18=r16,XEN_VIRT_UC_BIT, 15 // extract UC bit + ;; or r19=r17,r19 // insert PTE control bits into r19 - ;; mov r20=IA64_GRANULE_SHIFT<<2 - or r19=r19,r18 // set bit 4 (uncached) if the access was to UC region - ;; + ;; + dep r19=r18,r19,4,1 // set bit 4 (uncached) if the access was to UC region mov cr.itir=r20 ;; itc.i r19 // insert the TLB entry @@ -363,19 +361,17 @@ vmx_alt_dtlb_miss_1: ;; and r22=IA64_ISR_CODE_MASK,r20 // get the isr.code field tbit.nz p6,p7=r20,IA64_ISR_SP_BIT // is speculation bit on? - shr.u r18=r16,55 // move address bit 59 to bit 4 + extr.u r18=r16,XEN_VIRT_UC_BIT, 1 // extract UC bit and r19=r19,r16 // clear ed, reserved bits, and PTE control bits tbit.nz p9,p0=r20,IA64_ISR_NA_BIT // is non-access bit on? ;; - and r18=0x10,r18 // bit 4=address-bit(61) (p9)cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22 // check isr.code field dep r24=-1,r24,IA64_PSR_ED_BIT,1 or r19=r19,r17 // insert PTE control bits into r19 - ;; - or r19=r19,r18 // set bit 4 (uncached) if the access was to UC region + mov r20=IA64_GRANULE_SHIFT<<2 + ;; + dep r19=r18,r19,4,1 // set bit 4 (uncached) if the access was to UC region (p6)mov cr.ipsr=r24 - mov r20=IA64_GRANULE_SHIFT<<2 - ;; mov cr.itir=r20 ;; (p7)itc.d r19 // insert the TLB entry diff -r 7e8534c5598a -r 9ca15906b057 xen/arch/ia64/xen/ivt.S --- a/xen/arch/ia64/xen/ivt.S Tue Jun 12 06:07:46 2007 +0200 +++ b/xen/arch/ia64/xen/ivt.S Tue Jun 12 06:36:38 2007 +0200 @@ -119,12 +119,7 @@ ENTRY(itlb_miss) ;; /* If address belongs to VMM, go to alt tlb handler */ cmp.eq p6,p0=0x1e,r17 - ;; - cmp.eq.or p6,p0=0x1d,r17 (p6) br.cond.spnt late_alt_itlb_miss - ;; - mov pr = r31, 0x1ffff - ;; br.cond.sptk fast_tlb_miss_reflect ;; END(itlb_miss) @@ -141,8 +136,6 @@ ENTRY(dtlb_miss) ;; /* If address belongs to VMM, go to alt tlb handler */ cmp.eq p6,p0=0x1e,r17 - ;; - cmp.eq.or p6,p0=0x1d,r17 (p6) br.cond.spnt late_alt_dtlb_miss br.cond.sptk fast_tlb_miss_reflect ;; @@ -162,15 +155,13 @@ late_alt_itlb_miss: movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff) ;; extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl - and r19=r19,r16 // clear ed, reserved bits, and PTE control bits - shr.u r18=r16,55 // move address bit 59 to bit 4 - ;; - and r18=0x10,r18 // bit 4=address-bit(59) + and r19=r19,r16 // clear ed, reserved bits, and PTE ctrl bits + extr.u r18=r16,XEN_VIRT_UC_BIT,1 // extract UC bit + ;; cmp.ne p8,p0=r0,r23 // psr.cpl != 0? or r19=r17,r19 // insert PTE control bits into r19 ;; - or r19=r19,r18 // set bit 4 (uncached) if the access was to - // region 6 + dep r19=r18,r19,4,1 // set bit 4 (uncached) if access to UC area. (p8) br.cond.spnt page_fault ;; itc.i r19 // insert the TLB entry @@ -195,12 +186,11 @@ late_alt_dtlb_miss: extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl and r22=IA64_ISR_CODE_MASK,r20 // get the isr.code field tbit.nz p6,p7=r20,IA64_ISR_SP_BIT // is speculation bit on? - shr.u r18=r16,55 // move address bit 59 to bit 4 + extr.u r18=r16,XEN_VIRT_UC_BIT,1 // extract UC bit and r19=r19,r16 // clear ed, reserved bits, and // PTE control bits tbit.nz p9,p0=r20,IA64_ISR_NA_BIT // is non-access bit on? ;; - and r18=0x10,r18 // bit 4=address-bit(59) cmp.ne p8,p0=r0,r23 (p9) cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22 // check isr.code field (p8) br.cond.spnt page_fault @@ -212,22 +202,15 @@ late_alt_dtlb_miss: (p8) br.cond.sptk frametable_miss ;; #endif // If it is not a Xen address, handle it via page_fault. - // Note that 0xf000 (cached) and 0xe800 (uncached) addresses - // should be OK. extr.u r22=r16,59,5 ;; - cmp.eq p8,p0=0x1e,r22 -(p8) br.cond.spnt 1f - ;; - cmp.ne p8,p0=0x1d,r22 + cmp.ne p8,p0=0x1e,r22 (p8) br.cond.sptk page_fault ;; -1: dep r21=-1,r21,IA64_PSR_ED_BIT,1 or r19=r19,r17 // insert PTE control bits into r19 ;; - or r19=r19,r18 // set bit 4 (uncached) if the access was to - // region 6 + dep r19=r18,r19,4,1 // set bit 4 (uncached) if access to UC area (p6) mov cr.ipsr=r21 ;; (p7) itc.d r19 // insert the TLB entry diff -r 7e8534c5598a -r 9ca15906b057 xen/include/asm-ia64/xensystem.h --- a/xen/include/asm-ia64/xensystem.h Tue Jun 12 06:07:46 2007 +0200 +++ b/xen/include/asm-ia64/xensystem.h Tue Jun 12 06:36:38 2007 +0200 @@ -16,9 +16,8 @@ VMM memory space is protected by CPL for paravirtualized domains and by VA for VTi domains. VTi imposes VA bit 60 != VA bit 59 for VMM. */ -#define HYPERVISOR_VIRT_START 0xe800000000000000 -#define KERNEL_START 0xf000000004000000 -#define GATE_ADDR KERNEL_START +#define HYPERVISOR_VIRT_START 0xf000000000000000 +#define __IA64_UNCACHED_OFFSET 0xf200000000000000UL #define DEFAULT_SHAREDINFO_ADDR 0xf500000000000000 #define PERCPU_ADDR (DEFAULT_SHAREDINFO_ADDR - PERCPU_PAGE_SIZE) #ifdef CONFIG_VIRTUAL_FRAME_TABLE @@ -28,7 +27,11 @@ #define HYPERVISOR_VIRT_END 0xf800000000000000 #define PAGE_OFFSET __IA64_UL_CONST(0xf000000000000000) -#define __IA64_UNCACHED_OFFSET 0xe800000000000000UL + +#define XEN_VIRT_UC_BIT 57 + +#define KERNEL_START 0xf000000004000000 +#define GATE_ADDR KERNEL_START #define IS_VMM_ADDRESS(addr) ((((addr) >> 60) ^ ((addr) >> 59)) & 1)