# HG changeset patch
# User yamahata@xxxxxxxxxxxxx
# Date 1165824512 -32400
# Node ID 1f83fb7a050cab74aa4567ca20feee9e59d27227
# Parent  91be8436952d82eacd7e0db3aece8858c3a53150
patch from Matthew Chapman <matthewc@xxxxxxxxxxxxxxx>
http://lists.xensource.com/archives/html/xen-ia64-devel/2006-11/msg00349.html
The real VHPT insertion is done based on the machine PTE returned from
translate_domain_pte, which does the appropriate offset calculations.

However, the insertion into the one-entry TLB uses the original PTE, but
the page size has been reset to PAGE_SIZE [1].  Thus the entry in the
one-entry TLB incorrectly maps the PAGE_SIZE sub-page which was faulted
on to the PAGE_SIZE sub-page at the bottom of the superpage.

I think it makes most sense to simply use the original itir when
inserting into the single-entry TLB, as per attached patch.  I've moved
the vcpu_set_tr_entry calls up a level into vcpu_itc_d and vcpu_itc_i;
the third caller previously used the 4 flag to specify "don't do that".

[1] In fact, this is enforced twice, once in translate_domain_pte and
again in vcpu_itc_no_srlz.
PATCHNAME: tlb_insert_cache_fix

Signed-off-by: Isaku Yamahata <yamahata@xxxxxxxxxxxxx>

diff -r 91be8436952d -r 1f83fb7a050c xen/arch/ia64/xen/faults.c
--- a/xen/arch/ia64/xen/faults.c	Wed Jan 10 10:37:41 2007 -0700
+++ b/xen/arch/ia64/xen/faults.c	Mon Dec 11 17:08:32 2006 +0900
@@ -215,7 +215,7 @@ void ia64_do_page_fault(unsigned long ad
 		unsigned long m_pteval;
 		m_pteval = translate_domain_pte(pteval, address, itir,
 		                                &logps, &entry);
-		vcpu_itc_no_srlz(current, (is_data ? 2 : 1) | 4,
+		vcpu_itc_no_srlz(current, is_data ? 2 : 1,
 		                 address, m_pteval, pteval, logps, &entry);
 		if ((fault == IA64_USE_TLB && !current->arch.dtlb.pte.p) ||
 		    p2m_entry_retry(&entry)) {
diff -r 91be8436952d -r 1f83fb7a050c xen/arch/ia64/xen/vcpu.c
--- a/xen/arch/ia64/xen/vcpu.c	Wed Jan 10 10:37:41 2007 -0700
+++ b/xen/arch/ia64/xen/vcpu.c	Mon Dec 11 17:08:32 2006 +0900
@@ -2181,14 +2181,6 @@ vcpu_itc_no_srlz(VCPU * vcpu, u64 IorD, 
 	else
 		vhpt_insert(vaddr, pte, PAGE_SHIFT << 2);
 #endif
-	if (IorD & 0x4)		/* don't place in 1-entry TLB */
-		return;
-	if (IorD & 0x1) {
-		vcpu_set_tr_entry(&PSCBX(vcpu, itlb), mp_pte, ps << 2, vaddr);
-	}
-	if (IorD & 0x2) {
-		vcpu_set_tr_entry(&PSCBX(vcpu, dtlb), mp_pte, ps << 2, vaddr);
-	}
 }
 
 IA64FAULT vcpu_itc_d(VCPU * vcpu, u64 pte, u64 itir, u64 ifa)
@@ -2215,6 +2207,7 @@ IA64FAULT vcpu_itc_d(VCPU * vcpu, u64 pt
 		vcpu_flush_tlb_vhpt_range(ifa, logps);
 		goto again;
 	}
+	vcpu_set_tr_entry(&PSCBX(vcpu, dtlb), pte, itir, ifa);
 	return IA64_NO_FAULT;
 }
 
@@ -2241,6 +2234,7 @@ IA64FAULT vcpu_itc_i(VCPU * vcpu, u64 pt
 		vcpu_flush_tlb_vhpt_range(ifa, logps);
 		goto again;
 	}
+	vcpu_set_tr_entry(&PSCBX(vcpu, itlb), pte, itir, ifa);
 	return IA64_NO_FAULT;
 }