diff -r 0114b372dfae xen/arch/ia64/xen/faults.c
--- a/xen/arch/ia64/xen/faults.c	Wed Nov 22 10:13:31 2006 -0700
+++ b/xen/arch/ia64/xen/faults.c	Thu Nov 30 14:51:33 2006 +1100
@@ -215,7 +215,7 @@ void ia64_do_page_fault(unsigned long ad
 		unsigned long m_pteval;
 		m_pteval = translate_domain_pte(pteval, address, itir,
 		                                &logps, &entry);
-		vcpu_itc_no_srlz(current, (is_data ? 2 : 1) | 4,
+		vcpu_itc_no_srlz(current, is_data ? 2 : 1,
 		                 address, m_pteval, pteval, logps, &entry);
 		if ((fault == IA64_USE_TLB && !current->arch.dtlb.pte.p) ||
 		    p2m_entry_retry(&entry)) {
diff -r 0114b372dfae xen/arch/ia64/xen/vcpu.c
--- a/xen/arch/ia64/xen/vcpu.c	Wed Nov 22 10:13:31 2006 -0700
+++ b/xen/arch/ia64/xen/vcpu.c	Thu Nov 30 14:54:11 2006 +1100
@@ -2181,14 +2181,6 @@ vcpu_itc_no_srlz(VCPU * vcpu, u64 IorD, 
 	else
 		vhpt_insert(vaddr, pte, PAGE_SHIFT << 2);
 #endif
-	if (IorD & 0x4)		/* don't place in 1-entry TLB */
-		return;
-	if (IorD & 0x1) {
-		vcpu_set_tr_entry(&PSCBX(vcpu, itlb), mp_pte, ps << 2, vaddr);
-	}
-	if (IorD & 0x2) {
-		vcpu_set_tr_entry(&PSCBX(vcpu, dtlb), mp_pte, ps << 2, vaddr);
-	}
 }
 
 IA64FAULT vcpu_itc_d(VCPU * vcpu, u64 pte, u64 itir, u64 ifa)
@@ -2215,6 +2207,7 @@ IA64FAULT vcpu_itc_d(VCPU * vcpu, u64 pt
 		vcpu_flush_tlb_vhpt_range(ifa, logps);
 		goto again;
 	}
+	vcpu_set_tr_entry(&PSCBX(vcpu, dtlb), pte, itir, ifa);
 	return IA64_NO_FAULT;
 }
 
@@ -2241,6 +2234,7 @@ IA64FAULT vcpu_itc_i(VCPU * vcpu, u64 pt
 		vcpu_flush_tlb_vhpt_range(ifa, logps);
 		goto again;
 	}
+	vcpu_set_tr_entry(&PSCBX(vcpu, itlb), pte, itir, ifa);
 	return IA64_NO_FAULT;
 }