Hi Alex,
I (Doi.Tsunehisa) said:
> You (alex.williamson) said:
>>> +static int get_callback_irq(struct pci_dev *pdev)
>>> +{
>>> +#ifdef __ia64__
>>> + int irq;
>>> + for (irq = 0; irq < 16; irq++) {
>>> + if (isa_irq_to_vector_map[irq] == pdev->irq)
>>> + return irq;
>>
>> This should probably be isa_irq_to_vector(irq). Will the HVM PCI
>> device always use an ISA IRQ? Thanks,
>
> In my investigation, it always uses its value.
In qemu-dm code, it uses only PIC as interrupt controller, I think.
Other interrupt controller is masked as follow:
[tools/ioemu/hw/pc.c]
627 /* PC hardware initialisation */
628 static void pc_init1(uint64_t ram_size, ....
.....
650 /* init CPUs */
651 for(i = 0; i < smp_cpus; i++) {
652 env = cpu_init();
653 #ifndef CONFIG_DM
654 if (i != 0)
655 env->hflags |= HF_HALTED_MASK;
656 if (smp_cpus > 1) {
657 /* XXX: enable it in all cases */
658 env->cpuid_features |= CPUID_APIC;
659 }
660 #endif /* !CONFIG_DM */
661 register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
662 qemu_register_reset(main_cpu_reset, env);
663 #ifndef CONFIG_DM
664 if (pci_enabled) {
665 apic_init(env);
666 }
667 #endif /* !CONFIG_DM */
668 }
.....
818 #ifndef CONFIG_DM
819 if (pci_enabled) {
820 ioapic = ioapic_init();
821 }
822 #endif /* !CONFIG_DM */
823 isa_pic = pic_init(pic_irq_request, first_cpu);
824 #ifndef CONFIG_DM
825 pit = pit_init(0x40, 0);
826 pcspk_init(pit);
827 #endif /* !CONFIG_DM */
828 #ifndef CONFIG_DM
829 if (pci_enabled) {
830 pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic);
831 }
832 #endif /* !CONFIG_DM */
833
834 if (pci_enabled)
835 pci_xen_platform_init(pci_bus);
Thanks,
- Tsunehisa Doi
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