Thank you for your comments.
The race condition you pointed is in fact for ia64_do_page_fault:
fault = vcpu_translate(current,address,is_data,0,&pteval,&itir,&iha);
if (fault == IA64_NO_FAULT) {
pteval = translate_domain_pte(pteval,address,itir);
vcpu_itc_no_srlz(current,is_data?2:1,address,pteval,-1UL,(itir>>2)&0x3f);
return;
}
Between vcpu_translate and vcpu_itc_no_srlz, a ptc.ga must be taken into
account. I am looking for other possible races, but currently I don't see
other race point.
The obivous solution is a lock: between these two points, the tr_purge must be
delayed. We could add a 'tlb_protected' field in each vcpu.
This solution is quite simple but maybe heavy weight.
Any other solution ?
Tristan.
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