RE: [Xen-ia64-devel] [PATCH] tlb miss handler

["Tian, Kevin" <kevin.tian@xxxxxxxxx>]

>From: Isaku Yamahata
>Sent: 2006年2月3日 15:56
>
>I updated this patch for commit following the comments.
>I didn't optimize it and leave it to the future tuning phase.
>
>
>--
>Yamahata

Hi, Yamahata-san,
        Good catch here and several comments then:

- "alt itlb miss by a guest must be handled"
        Dom0 runs from the very start with vhpt enabled in all regions. There 
should be no alt itlb miss raised from dom0.

- It's better to copy whole original alt_dtlb_miss logic to dtlb miss handler, 
e.g:
        * Check for psr.cpl, speculation and non-access instructions are only 
tricks used in alt_dtlb_miss handler to ensure coherent memory attribute. So 
the better sequence is to check identity mapped hypervisor area first, and then 
check those three. For normal DTLB miss into other regions, those checks can be 
skipped then.

        * Why did you only handle cacheable (meant 0xf000....) area by identity 
mapping, whole leaving uncacheable (meant 0xe8000...) area to page_fault? That 
would low down the performance a lot.

        Simple way is like VTI domain to jump to alt_dtlb_miss code after 
necessary check upon identity mapping. Or you can merge the two handlers like 
your patch but  please keep necessary logic there. :-)

Thanks,
Kevin


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