diff -r c56a9805216a xen/arch/ia64/asm-offsets.c
--- a/xen/arch/ia64/asm-offsets.c	Tue Aug  9 10:32:52 2005
+++ b/xen/arch/ia64/asm-offsets.c	Tue Aug 16 17:28:33 2005
@@ -45,6 +45,8 @@
 	DEFINE(XSI_PSR_IC_OFS, offsetof(mapped_regs_t, interrupt_collection_enabled));
 	DEFINE(XSI_PSR_IC, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, interrupt_collection_enabled)));
 	DEFINE(XSI_PSR_I_OFS, offsetof(mapped_regs_t, interrupt_delivery_enabled));
+	DEFINE(XSI_IVA_OFS, offsetof(mapped_regs_t, iva));
+	DEFINE(XSI_IVA, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, iva)));
 	DEFINE(XSI_IIP_OFS, offsetof(mapped_regs_t, iip));
 	DEFINE(XSI_IIP, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, iip)));
 	DEFINE(XSI_IFA_OFS, offsetof(mapped_regs_t, ifa));
@@ -85,7 +87,6 @@
 	DEFINE(IA64_VCPU_META_RR0_OFFSET, offsetof (struct vcpu, arch.metaphysical_rr0));
 	DEFINE(IA64_VCPU_META_SAVED_RR0_OFFSET, offsetof (struct vcpu, arch.metaphysical_saved_rr0));
 	DEFINE(IA64_VCPU_BREAKIMM_OFFSET, offsetof (struct vcpu, arch.breakimm));
-	DEFINE(IA64_VCPU_IVA_OFFSET, offsetof (struct vcpu, arch.iva));
 	DEFINE(IA64_VCPU_IRR0_OFFSET, offsetof (struct vcpu, arch.irr[0]));
 	DEFINE(IA64_VCPU_IRR3_OFFSET, offsetof (struct vcpu, arch.irr[3]));
 	DEFINE(IA64_VCPU_INSVC3_OFFSET, offsetof (struct vcpu, arch.insvc[3]));
diff -r c56a9805216a xen/arch/ia64/hyperprivop.S
--- a/xen/arch/ia64/hyperprivop.S	Tue Aug  9 10:32:52 2005
+++ b/xen/arch/ia64/hyperprivop.S	Tue Aug 16 17:28:33 2005
@@ -257,8 +257,7 @@
 	st8 [r21]=r20 ;;
 	// leave cr.ifs alone for later rfi
 	// set iip to go to domain IVA break instruction vector
-	mov r22=IA64_KR(CURRENT);;
-	adds r22=IA64_VCPU_IVA_OFFSET,r22;;
+	adds r22=XSI_IVA_OFS-XSI_PSR_IC_OFS,r18 ;;
 	ld8 r23=[r22];;
 	movl r24=0x3000;;
 	add r24=r24,r23;;
@@ -428,7 +427,7 @@
 	st8 [r21]=r20 ;;
 	// leave cr.ifs alone for later rfi
 	// set iip to go to domain IVA break instruction vector
-	adds r22=IA64_VCPU_IVA_OFFSET,r19;;
+	adds r22=XSI_IVA_OFS-XSI_PSR_IC_OFS,r18 ;;
 	ld8 r23=[r22];;
 	movl r24=0x3000;;
 	add r24=r24,r23;;
@@ -581,8 +580,7 @@
 	st8 [r18]=r0;;
 	// FIXME: need to save iipa and isr to be arch-compliant
 	// set iip to go to domain IVA break instruction vector
-	mov r22=IA64_KR(CURRENT);;
-	adds r22=IA64_VCPU_IVA_OFFSET,r22;;
+	adds r22=XSI_IVA_OFS-XSI_PSR_IC_OFS,r18 ;;
 	ld8 r23=[r22];;
 	add r20=r20,r23;;
 	mov cr.iip=r20;;
@@ -920,7 +918,7 @@
 	st8 [r22]=r20 ;;
 #endif
 	// set iip to go to domain IVA break instruction vector
-	adds r22=IA64_VCPU_IVA_OFFSET,r30;;
+	adds r22=XSI_IVA_OFS-XSI_PSR_IC_OFS,r18 ;;
 	ld8 r23=[r22];;
 	movl r24=0x3000;;
 	add r24=r24,r23;;
diff -r c56a9805216a xen/arch/ia64/process.c
--- a/xen/arch/ia64/process.c	Tue Aug  9 10:32:52 2005
+++ b/xen/arch/ia64/process.c	Tue Aug 16 17:28:33 2005
@@ -195,7 +195,7 @@
 		}
 //printf("Delivering NESTED DATA TLB fault\n");
 		vector = IA64_DATA_NESTED_TLB_VECTOR;
-		regs->cr_iip = ((unsigned long) PSCBX(v,iva) + vector) & ~0xffUL;
+		regs->cr_iip = ((unsigned long) PSCB(v,iva) + vector) & ~0xffUL;
 		regs->cr_ipsr = (regs->cr_ipsr & ~DELIVER_PSR_CLR) | DELIVER_PSR_SET;
 // NOTE: nested trap must NOT pass PSCB address
 		//regs->r31 = (unsigned long) &PSCB(v);
@@ -221,7 +221,7 @@
 	PSCB(v,ifs) = 0;
 	PSCB(v,incomplete_regframe) = 0;
 
-	regs->cr_iip = ((unsigned long) PSCBX(v,iva) + vector) & ~0xffUL;
+	regs->cr_iip = ((unsigned long) PSCB(v,iva) + vector) & ~0xffUL;
 	regs->cr_ipsr = (regs->cr_ipsr & ~DELIVER_PSR_CLR) | DELIVER_PSR_SET;
 #ifdef CONFIG_SMP
 #error "sharedinfo doesn't handle smp yet"
diff -r c56a9805216a xen/arch/ia64/vcpu.c
--- a/xen/arch/ia64/vcpu.c	Tue Aug  9 10:32:52 2005
+++ b/xen/arch/ia64/vcpu.c	Tue Aug 16 17:28:33 2005
@@ -317,7 +317,7 @@
 
 UINT64 vcpu_get_ipsr_int_state(VCPU *vcpu,UINT64 prevpsr)
 {
-	UINT64 dcr = PSCBX(vcpu,dcr);
+	UINT64 dcr = PSCB(vcpu,dcr);
 	PSR psr = {0};
 
 	//printf("*** vcpu_get_ipsr_int_state (0x%016lx)...",prevpsr);
@@ -345,13 +345,13 @@
 //verbose("vcpu_get_dcr: called @%p\n",PSCB(vcpu,iip));
 	// Reads of cr.dcr on Xen always have the sign bit set, so
 	// a domain can differentiate whether it is running on SP or not
-	*pval = PSCBX(vcpu,dcr) | 0x8000000000000000L;
+	*pval = PSCB(vcpu,dcr) | 0x8000000000000000L;
 	return (IA64_NO_FAULT);
 }
 
 IA64FAULT vcpu_get_iva(VCPU *vcpu, UINT64 *pval)
 {
-	*pval = PSCBX(vcpu,iva) & ~0x7fffL;
+	*pval = PSCB(vcpu,iva) & ~0x7fffL;
 	return (IA64_NO_FAULT);
 }
 
@@ -470,13 +470,13 @@
 	// a domain can differentiate whether it is running on SP or not
 	// Thus, writes of DCR should ignore the sign bit
 //verbose("vcpu_set_dcr: called\n");
-	PSCBX(vcpu,dcr) = val & ~0x8000000000000000L;
+	PSCB(vcpu,dcr) = val & ~0x8000000000000000L;
 	return (IA64_NO_FAULT);
 }
 
 IA64FAULT vcpu_set_iva(VCPU *vcpu, UINT64 val)
 {
-	PSCBX(vcpu,iva) = val & ~0x7fffL;
+	PSCB(vcpu,iva) = val & ~0x7fffL;
 	return (IA64_NO_FAULT);
 }
 
diff -r c56a9805216a xen/include/asm-ia64/domain.h
--- a/xen/include/asm-ia64/domain.h	Tue Aug  9 10:32:52 2005
+++ b/xen/include/asm-ia64/domain.h	Tue Aug 16 17:28:33 2005
@@ -68,8 +68,6 @@
 	unsigned long dtlb_pte;
 	unsigned long irr[4];
 	unsigned long insvc[4];
-	unsigned long iva;
-	unsigned long dcr;
 	unsigned long itc;
 	unsigned long domain_itm;
 	unsigned long domain_itm_last;